A method for manufacturing a semiconductor device includes forming a plate structure over an isolation region. A drain electrode electrically connected to a drift region underlying the isolation region is formed, wherein the drain electrode is separated from a first location of the plate structure by a first distance along a central axis of an active area of the semiconductor device in a direction of a current flow between a source and a drain of the semiconductor device, the drain electrode is separated from a second location of the plate structure by a second distance along a line parallel to the central axis and within the active area. The first distance is less than the second distance.

A semiconductor device includes a semiconductor layer, an element isolation portion that is formed at the semiconductor layer and that defines an element region in the semiconductor layer, and a first contact that is formed in a linear shape along the element isolation portion in a plan view and that is electrically connected to the element isolation portion. The semiconductor device further includes a semiconductor substrate supporting the semiconductor layer and a buried layer formed so as to be contiguous to the semiconductor layer, and the element isolation portion may reach the semiconductor substrate through the buried layer from a front surface of the semiconductor layer.

A semiconductor device includes: a substrate; a source region and a drain region located in the substrate; a gate structure located in the substrate between the source region and the drain region; an insulating layer located between the gate structure and the drain region; a plurality of field plates located on the insulating layer, wherein the field plate closest to the gate structure is electrically connected to the source region; a first well region located in the substrate; a body contact region located in the first well region, wherein the body contact region is electrically connected to the source region and the field plate closest to the gate structure; and a first doped drift region located in the substrate, wherein the gate structure is located between the first well region and the first doped drift region, and the drain region is located in the first doped drift region.

A semiconductor structure, including a substrate, a first well, a second well, a first doped region, a second doped region, a first gate structure, a first insulating layer, and a first field plate structure. The first and second wells are disposed in the substrate. The first doped region is disposed in the first well. The second doped region is disposed in the second well. The first gate structure is disposed between the first and second doped regions. The first insulating layer covers a portion of the first well and a portion of the first gate structure. The first field plate structure is disposed on the first insulating layer, and it partially overlaps the first gate structure. Wherein the first field plate structure is segmented into a first partial field plate and a second partial field plate separated from each other along a first direction.

A semiconductor power device having shielded gate structure in an active area and trench field plate termination surrounding the active area is disclosed. A Zener diode connected between drain metal and source metal or gate metal for functioning as a SD or GD clamp diode. Trench field plate termination surrounding active area wherein only cell array located will not cause BV degradation when SD or GD poly clamped diode integrated.

Semiconductor devices, and more particularly semiconductor devices with improved edge termination structures are disclosed. A semiconductor device includes a drift region that forms part of an active region. An edge termination region is arranged along a perimeter of the active region and also includes a portion of the drift region. The edge termination region includes one or more sub-regions of an opposite doping type than the drift region and one or more electrodes may be capacitively coupled to the drift region by way of the one or more sub-regions. During a forward blocking mode for the semiconductor device, the one or more electrodes may provide a path that draws ions away from passivation layers that are on the edge termination region and away from the active region. In this manner, the semiconductor device may exhibit reduced leakage, particularly at higher operating voltages and higher associated operating temperatures.

A semiconductor device includes: a chip having a first main surface on one side and a second main surface on the other side; a first region of a first conduction type which is formed on the second main surface side in the chip; a second region of a second conduction type which is formed on the first main surface side of the chip and forms a pn-junction portion with the first region; a device region which is provided on the first main surface; a first groove structure including a first groove, a first insulating film, and a first polysilicon, and partitioning the device region; and a second groove structure including a second groove, a second insulating film, and a second polysilicon, and partitioning the device region on a device region side of the first groove structure.

A high voltage device is used as a lower switch in a power stage of a switching regulator. The high voltage device includes at least one lateral diffused metal oxide semiconductor (LDMOS) device, a first isolation region, a second isolation region, a third isolation region, and a current limiting device. The first isolation region is located in a semiconductor layer, and encloses the LDMOS device. The second isolation region has a first conductivity type, and encloses the first isolation region in the semiconductor layer. The third isolation region has a second conductivity type, and encloses the second isolation region in the semiconductor layer. The current limiting device is electrically connected to the second isolation region, and is configured to operably suppress a parasitic silicon controlled rectifier (SCR) from being turned on.

In an embodiment, a high frequency amplifying circuit includes a semiconductor device. The semiconductor device includes a semiconductor substrate having a bulk resistivity ρ≧100 Ohm.Math.cm, a front surface and a rear surface, an LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistor in the semiconductor substrate, and a RESURF structure comprising a doped buried layer arranged in the semiconductor substrate, spaced at a distance from the front surface and the rear surface, and coupled with at least one of a channel region and a body contact region of the LDMOS transistor.

A lateral double diffused MOS transistor including a substrate, a source region and a drain region disposed in the substrate, a first contact and a second contact connected to the source region and the drain region, respectively, a gate insulation layer and a gate electrode on the substrate, a first field plate extending from the gate electrode toward the drain region, a coupling gate disposed between the second contact and the first field plate on the substrate, the coupling gate having a coupling voltage by coupling operation with the second contact, and a second field plate disposed between the coupling gate and the first field plate on the substrate, the second field plate being electrically connected to the second field plate.