Disclosed are a receiver control circuit and a terminal. The receiver control circuit includes: a smart power amplifier module, a coder-decoder, and a receiver. The smart power amplifier module is electrically connected to the receiver by a first switch module. The first switch module includes a first switch component unit that is formed by a metal oxide semiconductor field-effect transistor (MOSFET). The first switch module further includes a first follower unit, where the first follower unit is configured to keep an unchanged voltage difference between a gate electrode of the MOSFET of the first switch component unit and a drain electrode thereof, and a gate electrode voltage of the MOSFET of the first switch component unit is greater than a drain electrode voltage thereof. The coder-decoder is electrically connected to the receiver by the second switch module. The second switch module includes a second switch component unit.

In some examples, a transistor includes a drain, a channel, and a gate. The channel surrounds the drain and has a channel length to width ratio. The gate is over the channel to provide an active channel region that has an active channel region length to width ratio that is greater than the channel length to width ratio.

A semiconductor device includes a substrate including an active pattern, a channel pattern on the active pattern and including semiconductor patterns, a source/drain pattern connected to the semiconductor patterns, a gate electrode on the semiconductor patterns, and a gate dielectric layer between the gate electrode and the semiconductor patterns. An inner spacer of the gate dielectric layer includes a horizontal portion between the high-k dielectric layer and the second semiconductor pattern, a vertical portion between the high-k dielectric layer and the source/drain pattern, and a corner portion between the horizontal portion and the vertical portion. A first thickness of the horizontal portion is less than a second thickness of the vertical portion. The second thickness of the vertical portion is less than a third thickness of the corner portion.

A circuit includes a P-channel transistor formed in a P-well and an N-channel transistor formed in an N-well. The first P-channel transistor has a control electrode connected to the P-well. The N-channel transistor is coupled in series with the P-channel transistor and has a control electrode connected to the N-well. Connecting the control electrodes of the P-channel and N-channel transistors to respective P-well and N-well effectively reduces crowbar current in the circuit.

One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.

The performance of a transistor is improved. The semiconductor device according to the embodiment includes: an insulating film (12) that separates an n-type transistor formation region (Tr1) and a p-type transistor formation region (Tr2) from each other, in which each of the n-type transistor formation region and the p-type transistor formation region includes a gate electrode (13) formed in a first direction on a semiconductor substrate (11), and source/drain regions (22) formed on both sides of the gate electrode in a second direction different from the first direction, and a distance from an interface between the insulating film and the source/drain regions to an end of the gate electrode in the second direction is different between the n-type transistor formation region and the p-type transistor formation region.

A semiconductor device includes a first and a second switching element, a first and a second conductive member, and a capacitor. The first switching element has a first element obverse surface and a first element reverse surface facing away from each other in a first direction. The second switching element has a second element obverse surface and a second element reverse surface facing away from each other in the first direction. The first and second conductive members are spaced apart in a second direction orthogonal to the first direction. The capacitor has a first and a second connection terminal. The first and second switching elements are connected in series, forming a bridge. The first and second connection terminals are electrically connected to opposite ends of the bridge. The capacitor and the first switching element are on the first conductive member, the second switching element on the second conductive member.

Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to integrated circuits with self-aligned tub architectures. Other embodiments may be described or claimed.

One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include: a gate structure between a pair of gate spacers within a dielectric layer and substantially surrounding a fin, wherein the gate structure is disposed adjacent to a channel region within the fin; and a source/drain contact extending within the dielectric layer to a source/drain region within a fin, the source/drain contact being separated from the gate structure by at least one gate spacer in the pair of gate spacers, wherein the channel region and the source/drain region provide electrical connection between the gate structure and the source/drain contact.

A chip includes a semiconductor substrate, a well region in the semiconductor substrate, and a Dynamic Threshold Metal-Oxide Semiconductor (DTMOS) transistor formed at a front side of the semiconductor substrate. The DTMOS transistor includes a gate electrode, and a source/drain region adjacent to the gate electrode. The source/drain region is disposed in the well region. A well pickup region is in the well region, and the well pickup region is at a back side of the semiconductor substrate. The well pickup region is electrically connected to the gate electrode.