A semiconductor device includes: a semiconductor layer having a first main surface in which a region for a first element is formed; and an element isolation portion configured to partition a first active region in the region for the first element. The first element includes: a first gate electrode, a first gate insulating film, a first-conduction-type first source region and a first-conduction-type first drain region, a first-conduction-type first source extension portion and a first-conduction-type first drain extension portion, and a second-conduction-type second source extension portion and a second-conduction-type second drain extension portion.

A transistor structure includes a semiconductor substrate, a gate structure, a channel region, and a first conductive region. The semiconductor substrate has a semiconductor surface. The gate structure is above the semiconductor surface, and a first concave is formed to reveal the gate structure. The channel region is under the semiconductor surface. The first conductive region is electrically coupled to the channel region, and a second concave is formed to reveal the first conductive region. A mask pattern in a photolithography process is used to define the first concave, and the mask pattern only defines one dimension length of the first concave.

A method of manufacturing a semiconductor structure and a semiconductor structure are disclosed. The method of manufacturing a semiconductor structure includes: providing a substrate; forming multiple support structures on the substrate, where the multiple support structures are arranged at intervals along a first direction, and a gate trench is formed between every two adjacent support structures; forming a gate structure in the gate trench; and removing a part of each of the support structures, such that each of retained support structures forms two isolation sidewalls spaced apart, the two isolation sidewalls are arranged on opposite sidewalls of the adjacent gate structures respectively, and a filling region is formed by the two isolation sidewalls.

Field-effect transistors, and integrated circuit devices containing such field-effect transistors, might include a semiconductor material having a first conductivity type, a first source/drain region having a second conductivity type, a second source/drain region having the second conductivity type, a first contact connected to the first source/drain region, a conductor overlying an active area of the semiconductor material and having an annular portion surrounding the first contact and a spur portion extending from an outer perimeter of the annular portion of the conductor, a second contact connected to the second source/drain region outside the annular portion of the conductor, a dielectric between the conductor and the active area, and a third contact overlying the active area and connected to the spur portion of the conductor.

A memory device includes a first string driver circuit and a second string driver circuit that are disposed laterally adjacent to each other in a length direction of a memory subsystem. The first and the second string driver circuits are disposed in an interleaved layout configuration such that the first connections of the first string driver are offset from the second connections of the second string driver in a width direction. For a same effective distance between the corresponding opposing first and second connections, a first pitch length corresponding to the interleaved layout configuration of the first and second string drivers is less by a predetermined reduction amount than a second pitch length between the first and second string drivers when disposed in a non-interleaved layout configuration in which each of the first connections is in-line with the corresponding second connection.

A method and apparatus include an n-doped layer having a first applied charge, and a p.sup.−-doped layer having a second applied charge. The p.sup.−-doped layer may be positioned below the n-doped layer. A p.sup.+-doped buffer layer may have a third applied charge and be positioned below the p.sup.−-doped layer. The respective charges at each layer may be determined based on a dopant level and a physical dimension of the layer. In one example, the n-doped layer, the p.sup.−-doped layer, and the p.sup.+-doped buffer layer comprise a lateral semiconductor manufactured from silicon carbide (SiC).

A semiconductor-on-insulator (SOI) transistor includes a semiconductor layer situated over a buried oxide layer, the buried oxide layer being situated over a substrate. The SOI transistor is situated in the semiconductor layer and includes a transistor body, gate fingers, source regions, and drain regions. The transistor body has a first conductivity type. The source regions and the drain regions have a second conductivity type opposite to the first conductivity type. A heavily-doped body-implant region has the first conductivity type and overlaps at least one source region. A common silicided region electrically ties the heavily-doped body-implant region to the at least one source region. The common silicided region can include a source silicided region, and a body tie silicided region situated over the heavily-doped body-implant region. The source silicided region can be separated from a drain silicided region by the gate fingers.

An integrated circuit includes a first diffusion area for a first type transistor. The first type transistor includes a first drain region and a first source region. A second diffusion area for a second type transistor is separated from the first diffusion area. The second type transistor includes a second drain region and a second source region. A gate electrode continuously extends across the first diffusion area and the second diffusion area in a routing direction. A first metallic structure is electrically coupled with the first source region. A second metallic structure is electrically coupled with the second drain region. A third metallic structure is disposed over and electrically coupled with the first and second metallic structures. A width of the first metallic structure is substantially equal to or larger than a width of the third metallic structure.

A method can include ion implanting with the gate mask to form first halo regions and ion implanting with the gate mask and first spacers as a mask to form second halo regions. The gate mask and first spacers can be removed, and an epitaxial layer formed. A dummy gate mask can be formed. Ion implanting with the dummy gate mask can from source-drain extensions. Second spacers can be formed on sides of the dummy gate mask. Ion implanting with the dummy gate mask and second spacers as a mask can form source and drain regions. A surface dielectric layer can be formed and planarized to expose a top of the dummy gate. The dummy gate can be removed to form gate openings between the second spacers. A hi-K dielectric layer and at least two gate metal layers within the gate opening. Related devices are also disclosed.

A semiconductor device comprises a vertical power device, such as a superjunction MOSFET, an IGBT, a diode, and the like, and a surface device that comprises one or more lateral devices that are electrically active along a top surface of the semiconductor device.