A semiconductor structure and a method for manufacturing same are provided. The semiconductor structure includes: a substrate, and a first transistor and a second transistor protruding from the substrate. The first transistor at least includes a first doped region and a second doped region arranged from bottom to top. The second transistor at least includes a third doped region and a fourth doped region arranged from bottom to top. Herein, the first doped region and the third doped region have a first conductivity type, the second doped region and the fourth doped region have a second conductivity type, and a breakdown voltage of the first transistor is smaller than a breakdown voltage of the second transistor.

Disclosed is a thin film transistor array comprising a substrate, a first thin film transistor on the substrate, and a second thin film transistor on the substrate, wherein the first thin film transistor includes a first active layer including an oxide semiconductor on the substrate, the first active layer includes a first channel portion, a first conductor portion, and a first middle portion between the first channel portion and the first conductor portion, the second thin film transistor includes a second active layer including an oxide semiconductor on the substrate, the second active layer includes a second channel portion, a second conductor portion, and a second middle portion between the second channel portion and the second conductor portion, and resistivity of the first conductor portion of the first thin film transistor is greater than resistivity of the second conductor portion of the second thin film transistor.

A display device and a manufacturing method thereof are disclosed. The display device includes a base substrate and at least one pixel circuit provided on the base substrate. The pixel circuit includes a driving transistor, a first transistor, and a second transistor; the base substrate includes a semiconductor body that can be doped, and a first conductive layer and a second conductive layer that are on the semiconductor body; the first transistor includes a first doped region in contact with the first electrode of the first transistor, and a second doped region in contact with a second electrode of the first transistor, and the first doped region of the first transistor and the second doped region of the first transistor are spaced apart from each other, have a same doping type, and are both in the semiconductor body.

A display device and a manufacturing method thereof are disclosed. The display device includes a base substrate and at least one pixel circuit provided on the base substrate. The pixel circuit includes a driving transistor, a first transistor, and a second transistor; the base substrate includes a semiconductor body that can be doped, and a first conductive layer and a second conductive layer that are on the semiconductor body; the first transistor includes a first doped region in contact with the first electrode of the first transistor, and a second doped region in contact with a second electrode of the first transistor, and the first doped region of the first transistor and the second doped region of the first transistor are spaced apart from each other, have a same doping type, and are both in the semiconductor body.

Provided is a semiconductor device having a top-gate structure resistant to creation of parasitic capacitance between a low-resistance region formed in a semiconductor layer and a gate electrode, and also provided region method for manufacturing the same and a display device including the same.

A TFT (100) has a low-resistance region, a portion of which has a first length (L1) ranging from a first position (P1) corresponding to an end of a gate insulating film to a region below a gate electrode (40), and the first length is substantially equal to a second length (L2) ranging from the first position (P1) to a second position (P2) corresponding to an end of the gate electrode (40). Thus, the overlap between the gate electrode (40) and either a source region (20s) or a drain region (20d) can be reduced, resulting in diminished parasitic capacitance.

An EL display having high operating performance and reliability is provided. LDD regions 15a through 15d of a switching TFT 201 formed in a pixel are formed such that they do not overlap gate electrodes 19a and 19b to provide a structure which is primarily intended for the reduction of an off-current. An LDD region 22 of a current control TFT 202 is formed such that it partially overlaps a gate electrode 35 to provide a structure which is primarily intended for the prevention of hot carrier injection and the reduction of an off-current. Appropriate TFT structures are thus provided depending on required functions to improve operational performance and reliability.

Failure light emission of an EL element due to failure film formation of an organic EL material in an electrode hole 46 is improved. By forming the organic EL material after embedding an insulator in an electrode hole 46 on a pixel electrode and forming a protective portion 41b, failure film formation in the electrode hole 46 can be prevented. This can prevent concentration of electric current due to a short circuit between a cathode and an anode of the EL element, and can prevent failure light emission of an EL layer.

A thin film transistor (10) may include a substrate (100); a buffer layer (300) on a surface of the substrate (100); an active layer (400) on a surface of the buffer layer (300) opposite from the substrate (100); a gate insulating layer (500) on a surface of the active layer (400) opposite from the substrate (100), and a gate (600) on a surface of the gate insulating layer (500) opposite from the substrate (100). A width of the active layer (400) may be smaller than a width of the gate (600), and an orthographic projection of the gate (600) on the substrate (100) may cover an orthographic projection of the active layer (400) on the substrate (100).

A semiconductor device and the method of manufacturing the same are provided. The semiconductor device comprises a well region, a first doped region, a drain region, a source region and a gate electrode. The first doped region of a first conductivity type is located at a first side within the well region. The drain region of the first conductivity type is within the first doped region. The source region of the first conductivity type is at a second side within the well region, wherein the second side being opposite to the first side. The gate electrode is over the well region and between the source region and the drain region. A surface of the drain region and a surface of the source region define a channel and the surface of the source region directly contacts the well region.

A semiconductor device and the method of manufacturing the same are provided. The semiconductor device comprises a well region, a first doped region, a drain region, a source region and a gate electrode. The first doped region of a first conductivity type is located at a first side within the well region. The drain region of the first conductivity type is within the first doped region. The source region of the first conductivity type is at a second side within the well region, wherein the second side being opposite to the first side. The gate electrode is over the well region and between the source region and the drain region. A surface of the drain region and a surface of the source region define a channel and the surface of the source region directly contacts the well region.