An IC structure includes a first SRAM cell and a second SRAM, where a layout of the second SRAM cell is a mirror image of that of the first SRAM cell about a vertical cell boundary therebetween. The first SRAM cell includes a first PD device and a second PD device disposed over a first fin and a second fin, respectively, where a portion of the first fin and a portion of the second fin corresponding to a channel region of the first and the second PD devices, respectively, each include a first stack of semiconductor layers defined by a channel width W1, a portion of the first fin and a portion of the second fin providing a source terminal of the first and the second PD devices, respectively, are each defined by a width W1′ that is enlarged with respect to the channel width W1.

Provided are oxide semiconductor transistors. The oxide semiconductor transistor includes a substrate, a channel layer arranged on the substrate and having a flat plate shape extending along one plane, a gate electrode facing a part of the channel layer, and a source region and a drain region separated from each other with the gate electrode therebetween, wherein the source region contacts three or more surfaces of the channel layer, and the drain region contacts three or more surfaces of the channel layer.

SRAM designs based on GAA transistors are disclosed that provide flexibility for increasing channel widths of transistors at scaled IC technology nodes and relax limits on SRAM performance optimization imposed by FinFET-based SRAMs. GAA-based SRAM cells described have active region layouts with active regions shared by pull-down GAA transistors and pass-gate GAA transistors. A width of shared active regions that correspond with the pull-down GAA transistors are enlarged with respect to widths of the shared active regions that correspond with the pass-gate GAA transistors. A ratio of the widths is tuned to obtain ratios of pull-down transistor effective channel width to pass-gate effective channel width greater than 1, increase an on-current of pull-down GAA transistors relative to an on-current of pass-gate GAA transistors, decrease a threshold voltage of pull-down GAA transistors relative to a threshold voltage of pass-gate GAA transistors, and/or increases a β ratio of an SRAM cell.

A semiconductor device is provided. The semiconductor device includes: an active pattern provided on a substrate and extending in a first direction; a pair of source/drain patterns provided on the active pattern and spaced apart from each other in the first direction; a plurality of channel layers vertically stacked and spaced apart from each other on the active pattern between the pair of source/drain patterns; a gate electrode extending in a second direction between the pair of source/drain patterns, the gate electrode being provided on the active pattern and surrounding the plurality of channel layers, and the second direction intersecting the first direction; and a gate spacer provided between the plurality of channel layers, and between the gate electrode and the pair of source/drain patterns. The gate spacer includes a plurality of first spacer patterns and a plurality of second spacer patterns that are alternately stacked on sidewalls of the pair of source/drain patterns.

A semiconductor device may include: an active pattern on a substrate and extending in a first direction; a plurality of source/drain patterns on the active pattern and spaced apart from each other in the first direction; a gate electrode between the plurality of source/drain patterns that crosses the active pattern and extends in a second direction intersecting the first direction; and a plurality of channel patterns stacked on the active pattern and configured to connect two or more of the source/drain patterns to each other. The channel patterns may be spaced apart from each other. Each of the channel patterns may include a first portion between the gate electrode and the source/drain patterns, and a plurality of second portions connected to the first portion and overlapped with the gate electrode in a direction perpendicular to a plane defined by an upper surface of the substrate.

A semiconductor device is provided. The semiconductor device includes a gate layer, a semiconductor layer and a ferroelectric layer disposed between the gate layer and the semiconductor layer. The semiconductor layer includes a first material containing a Group III element, a rare-earth element and a Group VI element, the ferroelectric layer includes a second material containing a Group III element, a rare-earth element and a Group V element and the gate layer includes a third material containing a Group III element and a rare-earth element. A method of fabricating a semiconductor device is also provided.

Provided are a thin film transistor capable of minimizing the level of a leakage current and a display apparatus including the same. The thin film transistor includes a buffer layer disposed over a substrate, and a semiconductor layer disposed over the buffer layer, wherein the semiconductor layer includes a first area doped with a first conductivity type and disposed adjacent to an upper surface of the semiconductor layer, a second area spaced apart from the first area, doped with the first conductivity type, and disposed adjacent to the upper surface of the semiconductor layer, a third area doped with a second conductivity type different from the first conductivity type and disposed under the first area, and a fourth area doped with the second conductivity type and disposed under the second area.

An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include a temperature sensor circuit and core circuitry. The temperature senor circuit may include at least one portion formed in a region other than the region that the IGFETs are formed as well as at least another portion formed in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming a portion of the temperature sensor circuit in regions below the IGFETs, an older process technology may be used and device size may be decreased and cost may be reduced.

A method for producing an ohmic contact on a crystallographic C-side of a silicon carbide substrate. The method includes: applying a layer stack to the crystallographic C-side of the silicon carbide substrate, the layer stack including at least one semiconducting layer containing germanium, and at least one metallic layer; and producing a point-by-point liquid phase of the layer stack, a surface of the layer stack being scanned using laser beams.

A semiconductor device that has low power consumption and is capable of performing arithmetic operation is provided. The semiconductor device includes first to third circuits and first and second cells. The first cell includes a first transistor, and the second cell includes a second transistor. The first and second transistors operate in a subthreshold region. The first cell is electrically connected to the first circuit, the first cell is electrically connected to the second and third circuits, and the second cell is electrically connected to the second and third circuits. The first cell sets current flowing from the first circuit to the first transistor to a first current, and the second cell sets current flowing from the second circuit to the second transistor to a second current. At this time, a potential corresponding to the second current is input to the first cell. Then, a sensor included in the third circuit supplies a third current to change a potential of the second wiring, whereby the first cell outputs a fourth current corresponding to the first current and the amount of change in the potential.