To provide a highly reliable memory device. A first insulator is formed over a substrate; a second insulator is formed over the first insulator; a third insulator is formed over the second insulator; an opening penetrating the first insulator, the second insulator, and the third insulator is formed; a fourth insulator is formed on the inner side of a side surface of the first insulator, a side surface of the second insulator, and a side surface of the third insulator, in the opening; an oxide semiconductor is formed on the inner side of the fourth insulator; the second insulator is removed; and a conductor is formed between the first insulator and the third insulator; and the fourth insulator is formed by performing, a plurality of times, a cycle including a first step of supplying a gas containing silicon and an oxidizing gas into a chamber where the substrate is placed, a second step of stopping the supply of the gas containing silicon into the chamber; and a third step of generating plasma containing the oxidizing gas in the chamber.

Methods of forming multi-tiered semiconductor devices are described, along with apparatus and systems that include them. In one such method, an opening is formed in a tier of semiconductor material and a tier of dielectric. A portion of the tier of semiconductor material exposed by the opening is processed so that the portion is doped differently than the remaining semiconductor material in the tier. At least substantially all of the remaining semiconductor material of the tier is removed, leaving the differently doped portion of the tier of semiconductor material as a charge storage structure. A tunneling dielectric is formed on a first surface of the charge storage structure and an intergate dielectric is formed on a second surface of the charge storage structure. Additional embodiments are also described.

A semiconductor memory device according to an embodiment, includes a plurality of semiconductor pillars extending in a first direction and being arranged along a second direction crossing the first direction, two interconnects extending in the second direction and being provided on two sides of the plurality of semiconductor pillars in a third direction crossing the first direction and the second direction, and an electrode film disposed between each of the semiconductor pillars and each of the interconnects. The two interconnects are drivable independently from each other.

A semiconductor memory device according to an embodiment, includes a semiconductor pillar extending in a first direction, a first electrode extending in a second direction crossing the first direction, a second electrode provided between the semiconductor pillar and the first electrode, a first insulating film provided between the semiconductor pillar and the second electrode, and a second insulating film provided between the first electrode and the second electrode. The second electrode includes a thin sheet portion disposed on the first electrode side, and a thick sheet portion disposed on the semiconductor pillar side. A length in the first direction of the thick sheet portion is longer than a length in the first direction of the thin sheet portion.

Disclosed is a method of manufacturing a semiconductor device, including: forming a slacked structure including first material layers and second material layers alternately stacked on each other; forming a pillar passing through the stacked structure, the pillar including a protruding portion protruding above an uppermost surface of the stacked structure; forming a conductive layer surrounding the protruding portion of the pillar; and forming a conductive pattern in contact with the protruding portion of the pillar by oxidizing a surface of the conductive layer.

A semiconductor device includes a substrate and a gate structure disposed over the substrate. The gate structure includes gate electrode layers and interlayer insulation structures that are alternately stacked with each other. The semiconductor device includes a dielectric structure disposed over the substrate to contact a sidewall surface of the gate structure, and a channel layer disposed on a sidewall surface of the dielectric structure over the substrate. Each of the interlayer insulation structure includes an insulation layer and a metal-organic framework layer that are disposed on the same plane.

Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.

A method of forming a semiconductor device includes forming, on a lower structure, a mold structure having interlayer insulating layers and gate layers alternately and repeatedly stacked. Each of the gate layers is formed of a first layer, a second layer, and a third layer sequentially stacked. The first and third layers include a first material, and the second layer includes a second material having an etch selectivity different from an etch selectivity of the first material. A hole formed to pass through the mold structure exposes side surfaces of the interlayer insulating layers and side surfaces of the gate layers. Gate layers exposed by the hole are etched, with an etching speed of the second material differing from an etching speed of the first material, to create recessed regions.

The present discloses relates to a semiconductor device and a method of manufacturing the semiconductor device. A semiconductor device includes a stacked structure including insulating layers and conductive layers stacked alternately with each other, a channel structure passing through at least a portion of the stacked structure, and a memory layer interposed between the conductive layers and the channel structure, wherein the memory layer includes a floating gate arranged between the conductive layers and the channel structure.

An embodiment of a memory device may comprise a vertical channel, a first memory cell formed on the vertical channel, a first wordline coupled to the first memory cell, a second memory cell formed on the vertical channel immediately above the first memory cell, a second wordline coupled to the second memory cell, and an airgap disposed between the first wordline and the second wordline. Other embodiments are disclosed and claimed.