Systems, apparatuses and methods may provide for memory cell technology comprising a control gate, a conductive channel, and a charge storage structure coupled to the control gate and the conductive channel, wherein the charge storage structure includes a polysilicon layer and a metal layer. In one example, the metal layer includes titanium nitride or other high effective work function metal.

A staggered memory cell architecture staggers memory cells on opposite sides of a shared bit line preserves memory cell density, while increasing the distance between such memory cells, thereby reducing the possibility of a disturb. In one implementation, the memory cells along a first side of a shared bit line are connected to a set of global word lines provided underneath the memory structure, while the memory cells on the other side of the shared bit line—which are staggered relative to the memory cells on the first side—are connected to global word lines above the memory structure.

Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

A staggered memory cell architecture staggers memory cells on opposite sides of a shared bit line preserves memory cell density, while increasing the distance between such memory cells, thereby reducing the possibility of a disturb. In one implementation, the memory cells along a first side of a shared bit line are connected to a set of global word lines provided underneath the memory structure, while the memory cells on the other side of the shared bit line—which are staggered relative to the memory cells on the first side—are connected to global word lines above the memory structure.

A first doped region extends from a top surface of a substrate to a first depth. An implant into the first doped region forms a second doped region of a second conductivity type. The second doped region extends from the top surface to a second depth that is less than the first depth. A split gate NVM structure has select and control gates over the second doped region. A drain region of the second conductivity type is formed adjacent to the select gate. A source region of the second conductivity type is formed adjacent to the control gate. Angled implants into the second doped region form a third doped region of the first conductivity type under a portion of the select gate and a fourth doped region of the first conductivity type under a portion of the control gate. The drain and source regions adjoin the third and fourth regions.

A charge trapping nonvolatile memory device includes a source region and a drain region disposed in an upper portion of a substrate and spaced apart from each other by a first trapping region, a channel region, and a second trapping region. A gate stack structure is disposed over the channel region. A first stack including a tunnel insulation layer, a first charge trap layer, and a first blocking insulation layer are disposed over the first trapping region. A second stack including a tunnel insulation layer, a second charge trap layer, and a second blocking insulation layer are disposed over the second trapping region. An interlayer insulation layer is disposed over the substrate and covers the gate stack structure. A first contact plug and a second contact plug penetrate the interlayer insulation layer and respectively contact the source region and the drain region. A third contact plug penetrates the interlayer insulation layer, contacts the gate stack structure, and overlaps with the first and the second charge trap layers.

A memory device that includes a pair of non-volatile memory cells, a first memory cell including a first memory gate and a first select gate, and a second memory cell including a second memory gate and a second select gate. The first and second memory cells share a source line, and the first and second memory gates are not connected to one another.

An improvement is achieved in the performance of a semiconductor device having a nonvolatile memory. A first memory cell includes a first control gate electrode and a first memory gate electrode which are formed over a semiconductor substrate to be adjacent to each other. A second memory cell includes a second control gate electrode and a second memory gate electrode which are formed over the semiconductor substrate to be adjacent to each other. A width of a sidewall spacer formed on a side of the second memory gate electrode opposite to a side thereof where the second memory gate electrode is adjacent to the second control gate electrode is smaller than a width of another sidewall spacer formed on a side of the first memory gate electrode opposite to a side thereof where the first memory gate electrode is adjacent to the first control gate electrode. A threshold voltage of a first memory transistor including the first memory gate electrode in a neutral state is different a threshold voltage of a second memory transistor including the second memory gate electrode in the neutral state.

A memory device includes a gate electrode, a gate insulating layer formed on the gate electrode, a tunneling insulating layer stacked on the gate insulating layer, a channel layer stacked on the tunneling insulating layer, and a source electrode and a drain electrode formed on the channel layer to be spaced apart from each other. The tunneling insulating layer suppresses tunneling of charges from any one of the channel layer and the gate electrode by a voltage applied to each of the gate electrode and the drain electrode, and a density of tunneled charges is set according to the voltage applied to the drain electrode to output and store multiple current levels.