A semiconductor test structure includes a field-effect transistor and a metal connection structure. The field-effect transistor includes a substrate with first doping type, a gate located on a surface of the substrate, and a source region with a second doping type and a drain region with the second doping type in the substrate, the source region and the drain region are located on two sides of the gate, respectively. The metal connection structure is connected with the gate; the metal connection structure forms a Schottky contact with the substrate.

The present disclosure relates to a semiconductor device with a contact structure and a method for preparing the semiconductor device. The semiconductor device includes a source/drain structure disposed over a semiconductor substrate, and a dielectric layer disposed over the source/drain structure. The semiconductor device also includes a polysilicon stack disposed over the source/drain structure and surrounded by the dielectric layer. The polysilicon stack includes a first polysilicon layer and a second polysilicon layer disposed over the first polysilicon layer. The first polysilicon layer is undoped, and the second polysilicon layer is doped. The semiconductor device further includes a contact structure disposed directly over the polysilicon stack and surrounded by the dielectric layer.

A power SiC MOSFET with a built-in Schottky rectifier provides advantages of including a Schottky rectifier, such as avoiding bipolar degradation, while reducing a parasitic capacitive charge and related power losses, as well as system cost. A lateral built-in channel layer may enable lateral spacing of the MOSFET gate oxide from a high electric field at the Schottky contact, while also providing current limiting during short-circuit events.

A reverse blocking gallium nitride (GaN) high electron mobility transistor includes, sequentially stacked from bottom to top, a substrate, a nucleation layer, a buffer layer, a barrier layer, a dielectric layer. The buffer layer and the barrier layer form a heterojunction structure. The barrier layer is provided with at least two p-GaN structures. The barrier layer is provided with a source metal at one end and a drain metal at the other end, source metal forms ohmic contact and drain metal forms Schottky contact with AlGaN barrier, respectively. In forward conduction, the two-dimensional electron gas below the spaced p-GaN structure connected to the drain metal is conductive, and a turn-on voltage of the device is low. During reverse blocking, the two-dimensional electron gas at the spaced p-GaN structure is rapidly depleted under reverse bias, to form a depletion region, so that the blocking capability of the device is improved.

The present disclosure generally relates to an apparatus for high density memory with integrated logic. A three terminal ReRAM device, which includes a p-n junction and a Schottky barrier, that can switch from a low resistive state to a high resistive state is provided. The Schottky transistor memory device includes a source region, a drain region, a first p-type or n-type oxide layer disposed between the source and drain regions, a second p-type or n-type oxide layer, and a gate electrode. As voltage is applied to the gate electrode, the Schottky barrier breaks down, leading to the formation of a filament. The filament is non-volatile and short-circuits the reverse-biased barrier, keeping the device in a low resistance state. Removing the filament by reversing the polarity of the voltage switches the device back to a high resistance state, allowing for the memory state to be readout through the gate electrode.

An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

An electrical device in which an interface layer is disposed in between and in contact with a conductor and a semiconductor.

A power SiC MOSFET with a built-in Schottky rectifier provides advantages of including a Schottky rectifier, such as avoiding bipolar degradation, while reducing a parasitic capacitive charge and related power losses, as well as system cost. A lateral built-in channel layer may enable lateral spacing of the MOSFET gate oxide from a high electric field at the Schottky contact, while also providing current limiting during short-circuit events.

A charge balance (CB) field-effect transistor (FET) device may include a CB layer defined in a first epitaxial (epi) layer having a first conductivity type. The CB layer may include a set of CB regions having a second conductivity type. The CB FET device may further include a device layer defined in a device epi layer having the first conductivity type disposed on the CB layer. The device layer may include a highly-doped region having the second conductivity type. The CB FET device may also include a CB bus region having the second conductivity type that extends between and electrically couples a CB region of the set of CB regions of the CB layer to the highly-doped region of the device layer.

The present disclosure relates to a semiconductor device with a contact structure and a method for preparing the semiconductor device. The semiconductor device includes a source/drain structure disposed over a semiconductor substrate, and a dielectric layer disposed over the source/drain structure. The semiconductor device also includes a polysilicon stack disposed over the source/drain structure and surrounded by the dielectric layer. The polysilicon stack includes a first polysilicon layer and a second polysilicon layer disposed over the first polysilicon layer. The first polysilicon layer is undoped, and the second polysilicon layer is doped. The semiconductor device further includes a contact structure disposed directly over the polysilicon stack and surrounded by the dielectric layer.