An electronic device for storing, controlling and manipulating electron or hole spin based semiconductor qubits, the device including an electrically insulating layer and on a front face of the insulating layer, a trapping structure for electrons or holes which includes: a channel portion including at least one layer portion of semiconductor material, as well as a plurality of gates distributed for trapping at least one electron or hole in the channel portion, and on the back side of the insulating layer, an electrical track extending parallel to the insulating layer, for generating an oscillating magnetic field acting on the at least one electron or hole trapped in the trapping structure.

An electronic device for storing, controlling and manipulating electron or hole spin based semiconductor qubits, the device including an electrically insulating layer and on a front face of the insulating layer, a trapping structure for electrons or holes which includes: a channel portion including at least one layer portion of semiconductor material, as well as a plurality of gates distributed for trapping at least one electron or hole in the channel portion, and on the back side of the insulating layer, an electrical track extending parallel to the insulating layer, for generating an oscillating magnetic field acting on the at least one electron or hole trapped in the trapping structure.

An approach to provide a structure of a double magnetic tunnel junction device with two spacers that includes a bottom magnetic tunnel junction stack, a spin conducting layer on the bottom magnetic tunnel junction stack, a top magnetic tunnel junction stack on the spin conduction layer, a first dielectric spacer on sides of the top magnetic tunnel junction stack and a portion of a top surface of the spin conduction layer, and a second dielectric spacer on the first spacer. The double magnetic tunnel device includes the top magnetic tunnel junction stack with a width that is less than the width of the bottom magnetic tunnel junction stack.

There is provided a magnetoresistance effect element includes: a channel layer that extends in a first direction; a recording layer which includes a film formed from a ferromagnetic material, of which a magnetization state is changed to one of two or greater magnetization states, and which is formed on the channel layer; a non-magnetic layer that is provided on a surface of the recording layer; a reference layer which is provided on a surface of the non-magnetic layer, which includes a film formed from a ferromagnetic material, and of which a magnetization direction is fixed; a terminal pair that includes a first terminal and a second terminal which are electrically connected to the channel layer with an interval in the first direction, and to which a current pulse for bringing the recording layer to any one magnetization state with a plurality of pulses is input by flowing a current to the channel layer between the first terminal and the second terminal; and a third terminal that is electrically connected to the reference layer.

Disclosed herein are quantum dot devices and techniques. In some embodiments, a quantum computing processing device may include a quantum well stack, an array of quantum dot gate electrodes above the quantum well stack, and an associated array of selectors above the array of quantum dot gate electrodes. The array of quantum dot gate electrodes and the array of selectors may each be arranged in a grid.

A memory element including a layered structure including a memory layer having magnetization perpendicular to a film face in which a direction of the magnetization is changed depending on information stored therein, a magnetization-fixed layer having magnetization perpendicular to the film face, which becomes a base of the information stored in the memory layer, and an intermediate layer that is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer.

A memory element including a layered structure including a memory layer having magnetization perpendicular to a film face in which a direction of the magnetization is changed depending on information stored therein, a magnetization-fixed layer having magnetization perpendicular to the film face, which becomes a base of the information stored in the memory layer, and an intermediate layer that is formed of a non-magnetic material and is provided between the memory layer and the magnetization-fixed layer.

The invention comprises a method of forming a magnetic free layer having a (100) texture and a novel magnetic pinning structure having a (100) textured or cube-textured reference layer through a non-epitaxial texturing approach so that an excellent coherent tunneling effect is achieved in a pMTJ element due to its texture structure of Fe or CoFe BCC (100)/MgO rocksalt (100)/Fe or CoFe BCC (100). The invention also discloses a pMTJ element comprising a soft-magnetic adjacent layer having at least one high-permeability material layer having a near-zero magnetostriction. Correspondingly, a high MR ratio and a coherent domain reversal of the magnetic free layer can be achieved for perpendicular spin-transfer-torque magnetic-random-access memory (pSTT-MRAM) using perpendicular magnetoresistive elements as basic memory cells which potentially replace the conventional semiconductor memory used in electronic chips, especially mobile chips for power saving and non-volatility.

A magnetic multilayer film for a magnetic memory element includes an amorphous heavy metal layer having a multilayer structure in which a plurality of first layers containing Hf alternate repeatedly with a plurality of second layers containing a heavy metal excluding Hf; and a recording layer that includes a ferromagnetic layer and that is adjacent to the heavy metal layer, the ferromagnetic layer having a variable magnetization direction.

A semiconductor structure includes: a Magnetic Random Access Memory (MRAM) cell, including a bottom electrode, a Magnetic Tunnel Junction (MTJ) stack and a top electrode; an insulating layer covering a sidewall partially and a top surface of the MRAM cell; a first dielectric layer, a stop layer and a second dielectric layer sequentially stacked on the insulating layer; and a top electrode contact hole penetrating through the second dielectric layer, the stop layer, the first dielectric layer and the insulating layer, and extending to the top electrode, where the top electrode contact hole includes a first portion and a second portion connected with each other in the stop layer, and a radial width of the second portion in contact with the top electrode is gradually decreased with an increase in a depth of the top electrode contact hole. Method for manufacturing the structure and semiconductor memory are also provided.