The first layer is located on the first electrode and has the first conductivity type. The second layer is located on the first layer and has the second conductivity type. The third layer is located on the second layer. The second electrode is located on the third layer. The fourth layer is located between the second layer and the third layer, and has the second conductivity type. The third layer includes the first portion and the second portion. The first portion has the second conductivity type and has a peak value of an impurity concentration higher than the peak value of the impurity concentration in the second layer. The second portion has the first conductivity type. The area of the second portion accounts for not less than 20% and not more than 95% of the total area of the first portion and the second portion.

A semiconductor device includes a composite pn-junction structure in a semiconductor substrate, wherein the composite pn-junction structure has a first junction grading coefficient m.sub.1, with m.sub.1≥0.50. The composite pn-junction structure includes a first partial pn-junction structure and a second partial pn-junction structure, wherein the first partial pn-junction structure has a first partial junction grading coefficient m.sub.11, and wherein the second partial pn-junction structure has a second partial junction grading coefficient m.sub.12. The first partial junction grading coefficient m.sub.11 is different to the second partial junction grading coefficient m.sub.12, with m.sub.11≠m.sub.12. At least one of the first and second partial junction grading coefficients m.sub.11, m.sub.12 is greater than 0.50, with m.sub.11 and/or m.sub.12>0.50. The first junction grading coefficient m.sub.1 of the composite pn-junction structure is based on a combination of the first and second partial junction grading coefficients m.sub.11, m.sub.12.

A semiconductor device having first through third layers. The first layer has a conductivity type that is different from a conductivity type of the second layer. A peak value of an impurity concentration of a portion of the third layer is greater than a peak value of an impurity concentration of the second layer. The semiconductor device allows a decrease in the forward voltage drop and also allows an improvement of the safe operating area tolerance. Thus, it is possible to decrease the forward voltage drop, improve the maximum reverse voltage, and suppress oscillations at the time of recovery.

A semiconductor device includes a substrate having a first conductivity type, a high-voltage well having a second conductivity type and formed in the substrate, a drift region formed in the high-voltage well, a drain region formed in the high-voltage well and spaced apart from the drift region, and a buried region having the first conductivity type formed in the high-voltage well between the drift region and the drain region.

A semiconductor device includes “n” pairs of pn-junction structures, wherein the i-th pair includes two pn-junction structures of the i-th type, wherein the two pn-junction structures of the i-th type are anti-serially connected, wherein the pn-junction structure of the i-th type has an i-th junction grading coefficient m.sub.i. A first pair of the n pairs of pn-junction structures has a first junction grading coefficient m.sub.1 and a second pair of the n pairs of pn-junction structures has a second junction grading coefficient m.sub.2. The junction grading coefficients m.sub.1, m.sub.2 are adjusted to result in generation of a spurious third harmonic signal of the semiconductor device with a signal power level, which is at least 10 dB lower than a reference signal power level of the spurious third harmonic signal obtained for a reference case in which the first and second junction grading coefficients m.sub.1, m.sub.2 are 0.25.

A semiconductor having a n-doped cathode layer, a p-doped anode layer, and a drift region, arranged between the cathode layer and the anode layer, with a dopant concentration of at most 8.Math.10.sup.15 cm.sup.−3. The drift region has a lightly n-doped drift layer and a lightly p-doped drift layer, arranged between the n-doped drift layer and the anode layer, both drift layers each have a layer thickness of at least 5 μm. The cathode layer has a first section with a dopant concentration of at least 1.Math.10.sup.17 cm.sup.−3 and a second section, arranged between the first section and the drift region, the second section has a layer thickness of at least 1 μm and a dopant concentration gradient that increases in the direction of the first section up to a dopant concentration maximum. The dopant concentration maximum is smaller or equal to the dopant concentration of the first section.

A semiconductor device including a first conductivity-type layer into which first conductivity-type impurities are introduced, a second conductivity-type layer into which second conductivity-type impurities are introduced, the second conductivity-type impurities being different in polarity from the first conductivity-type impurities, and an intermediate layer that is sandwiched between the first conductivity-type layer and the second conductivity-type layer, and does not include the first conductivity-type impurities or the second conductivity-type impurities, or includes the first conductivity-type impurities or the second conductivity-type impurities at a concentration lower than a concentration of the first conductivity-type impurities in the first conductivity-type layer or the second conductivity-type impurities in the second conductivity-type layer, the first conductivity-type layer, the intermediate layer, and the second conductivity-type layer being stacked in a thickness direction of a semiconductor substrate inside the semiconductor substrate.

A semiconductor having a n-doped cathode layer, a p-doped anode layer, and a drift region, arranged between the cathode layer and the anode layer, with a dopant concentration of at most 8.Math.10.sup.15 cm.sup.−3. The drift region has a lightly n-doped drift layer and a lightly p-doped drift layer, arranged between the n-doped drift layer and the anode layer, both drift layers each have a layer thickness of at least 5 μm. The cathode layer has a first section with a dopant concentration of at least 1.Math.10.sup.17 cm.sup.−3 and a second section, arranged between the first section and the drift region, the second section has a layer thickness of at least 1 μm and a dopant concentration gradient that increases in the direction of the first section up to a dopant concentration maximum. The dopant concentration maximum is smaller or equal to the dopant concentration of the first section.

A semiconductor device includes “n” pairs of pn-junction structures, wherein the i-th pair includes two pn-junction structures of the i-th type, wherein the two pn-junction structures of the i-th type are anti-serially connected, wherein the pn-junction structure of the i-th type has an i-th junction grading coefficient m.sub.i. A first pair of the n pairs of pn-junction structures has a first junction grading coefficient m.sub.1 and a second pair of the n pairs of pn-junction structures has a second junction grading coefficient m.sub.2. The junction grading coefficients m.sub.1, m.sub.2 are adjusted to result in generation of a spurious third harmonic signal of the semiconductor device with a signal power level, which is at least 10 dB lower than a reference signal power level of the spurious third harmonic signal obtained for a reference case in which the first and second junction grading coefficients m.sub.1, m.sub.2 are 0.25.

A semiconductor device has a semiconductor substrate that includes an element range and a peripheral range. The semiconductor substrate includes: a body region disposed within the element range; a p-type deep region that is disposed from the element range through the peripheral range, is distributed from an upper surface of the semiconductor substrate to a position deeper than a lower end of each gate trench, and involves end gate trench; and a p-type voltage resistance region that is disposed within the peripheral range, and is distributed from the upper surface to a position shallower than a lower end of the p-type deep region. A p-type impurity concentration within the p-type deep region is increased in the direction from the body region toward the p-type voltage resistance region.