According to an aspect of the present disclosure, a semiconductor device includes a substrate including an IGBT region, and a diode region, a surface electrode provided on a top surface of the substrate and a back surface electrode provided on a back surface on an opposite side to the top surface of the substrate, wherein the diode region includes a first portion formed to be thinner than the IGBT region by the top surface of the substrate being recessed, and a second portion provided on one side of the first portion and thicker than the first portion.

According to an aspect of the present disclosure, a semiconductor device includes a substrate including an IGBT region, and a diode region, a surface electrode provided on a top surface of the substrate and a back surface electrode provided on a back surface on an opposite side to the top surface of the substrate, wherein the diode region includes a first portion formed to be thinner than the IGBT region by the top surface of the substrate being recessed, and a second portion provided on one side of the first portion and thicker than the first portion.

We disclose a III-nitride semiconductor based heterojunction power device comprising: a first heterojunction transistor formed on a substrate, the first heterojunction transistor comprising: a first III-nitride semiconductor region formed over the substrate, wherein the first III-nitride semiconductor region comprises a first heterojunction comprising at least one two dimensional carrier gas; a first terminal operatively connected to the first III-nitride semiconductor region; a second terminal laterally spaced from the first terminal and operatively connected to the first III-nitride semiconductor region; a first plurality of highly doped semiconductor regions of a first polarity formed over the first III-nitride semiconductor region, the first plurality of highly doped semiconductor regions being formed between the first terminal and the second terminal; a first gate region operatively connected to the first plurality of highly doped semiconductor regions; and a second heterojunction transistor formed on the substrate. The second heterojunction transistor comprises: a second III-nitride semiconductor region formed over the substrate, wherein the second III-nitride semiconductor region comprises a second heterojunction comprising at least one two dimensional carrier gas; a third terminal operatively connected to the second III-nitride semiconductor region; a fourth terminal laterally spaced from the third terminal in the first dimension and operatively connected to the second III-nitride semiconductor region; a second gate region being formed over the second III-nitride semiconductor region, and between the third terminal and the fourth terminal. One of the first and second heterojunction transistors is an enhancement mode field effect transistor and the other of the first and second heterojunction transistors is a depletion mode field effect transistor.

A method and apparatus include an n-doped layer having a first applied charge, and a p.sup.−-doped layer having a second applied charge. The p.sup.−-doped layer may be positioned below the n-doped layer. A p.sup.+-doped buffer layer may have a third applied charge and be positioned below the p.sup.−-doped layer. The respective charges at each layer may be determined based on a dopant level and a physical dimension of the layer. In one example, the n-doped layer, the p.sup.−-doped layer, and the p.sup.+-doped buffer layer comprise a lateral semiconductor manufactured from silicon carbide (SiC).

A method and apparatus include an n-doped layer having a first applied charge, and a p.sup.−-doped layer having a second applied charge. The p.sup.−-doped layer may be positioned below the n-doped layer. A p.sup.+-doped buffer layer may have a third applied charge and be positioned below the p.sup.−-doped layer. The respective charges at each layer may be determined based on a dopant level and a physical dimension of the layer. In one example, the n-doped layer, the p.sup.−-doped layer, and the p.sup.+-doped buffer layer comprise a lateral semiconductor manufactured from silicon carbide (SiC).

There is disclosed the integration of a Schottky diode with a MOSFET, more in detail there is a free-wheeling Schottky diode and a power MOSFET on top of a buried grid material structure. Advantages of the specific design allow the whole surface area to be used for MOSFET and Schottky diode structures, the shared drift layer is not limited by Schottky diode or MOSFET design rules and therefore, one can decrease the thickness and increase the doping concentration of the drift layer closer to a punch through design compared to the state of the art. This results in higher conductivity and lower on-resistance of the device with no influence on the voltage blocking performance. The integrated device can operate at higher frequency. The risk for bipolar degradation is avoided.

A Schottky barrier diode includes a semiconductor substrate made of gallium oxide, a drift layer made of gallium oxide and formed on the semiconductor substrate, an anode electrode brought into Schottky contact with the drift layer, a cathode electrode brought into ohmic contact with the semiconductor substrate, an insulating film covering the inner wall of a trench formed in the drift layer, and a protective film covering the anode electrode, wherein a part of the protective film is embedded in the trench. The part of the protective film is thus embedded in the trench, so that adhesion performance between the anode electrode and protective film is enhanced. This makes it possible to prevent peeling at the boundary between the anode electrode and the protective film.

A Schottky barrier diode includes a semiconductor substrate made of gallium oxide, a drift layer made of gallium oxide and formed on the semiconductor substrate, an anode electrode brought into Schottky contact with the drift layer, a cathode electrode brought into ohmic contact with the semiconductor substrate, an insulating film covering the inner wall of a trench formed in the drift layer, and a protective film covering the anode electrode, wherein a part of the protective film is embedded in the trench. The part of the protective film is thus embedded in the trench, so that adhesion performance between the anode electrode and protective film is enhanced. This makes it possible to prevent peeling at the boundary between the anode electrode and the protective film.

A wide gap semiconductor device has: a wide gap semiconductor layer; and a metal layer 20 provided on the wide gap semiconductor layer. The metal layer 20 has a single crystal layer 21 in an interface region at an interface with the wide gap semiconductor layer. When it is assumed that a lattice constant, in an equilibrium state, of a metal constituting the metal layer 20 is L, the single crystal layer 21 in the interface region includes a first region in which a lattice constant L1 is smaller than L by 1.5% to 8%.

A wide gap semiconductor device has: a wide gap semiconductor layer; and a metal layer 20 provided on the wide gap semiconductor layer. The metal layer 20 has a single crystal layer 21 in an interface region at an interface with the wide gap semiconductor layer. When it is assumed that a lattice constant, in an equilibrium state, of a metal constituting the metal layer 20 is L, the single crystal layer 21 in the interface region includes a first region in which a lattice constant L1 is smaller than L by 1.5% to 8%.