A semiconductor component, in particular for a varactor, having at least one first semiconductor layer and a second semiconductor layer. At least two identical surface electrodes are arranged directly or indirectly on the second semiconductor layer facing away from the first semiconductor layer in order to form two anti-serially connected diodes. The surface electrodes are arranged in an interacting manner such that a load carrier zone which forms the common counter electrode for the surface electrodes is arranged in the first semiconductor layer at least in the operating state, and at least one control contact for controlling the potential of the load carrier zone is provided in a region of the load carrier zone on the second semiconductor layer face facing away from the first semiconductor layer. The load carrier zone produces a continuous electric connection from the counter electrode to the at least one control contact at least in the operating state, and the load carrier zone protrudes beyond the surface electrodes in a projection onto the rear face of the semiconductor component.

A semiconductor component, in particular for a varactor, having at least one first semiconductor layer and a second semiconductor layer. At least two identical surface electrodes are arranged directly or indirectly on the second semiconductor layer facing away from the first semiconductor layer in order to form two anti-serially connected diodes. The surface electrodes are arranged in an interacting manner such that a load carrier zone which forms the common counter electrode for the surface electrodes is arranged in the first semiconductor layer at least in the operating state, and at least one control contact for controlling the potential of the load carrier zone is provided in a region of the load carrier zone on the second semiconductor layer face facing away from the first semiconductor layer. The load carrier zone produces a continuous electric connection from the counter electrode to the at least one control contact at least in the operating state, and the load carrier zone protrudes beyond the surface electrodes in a projection onto the rear face of the semiconductor component.

A varactor structure includes a substrate. A first and second gate structure are disposed on the substrate. The first and second gate structures each include a base portion and a plurality of line portions connected thereto. The line portions of each of the first and second gate structures is alternately arranged. A meander diffusion region is formed in the substrate and surrounds the line portions. A first set of contact plugs is planned with at least two columns or rows and disposed on the base portions of the first and second gate structures. A second set of contact plugs is planned with at least two columns or rows and disposed on the meander diffusion region. A first conductive layer is disposed on a top end of the first set of contact plugs. A second conductive layer is disposed on a top end of the second set of contact plugs.

A varactor structure includes a substrate. A first and second gate structure are disposed on the substrate. The first and second gate structures each include a base portion and a plurality of line portions connected thereto. The line portions of each of the first and second gate structures is alternately arranged. A meander diffusion region is formed in the substrate and surrounds the line portions. A first set of contact plugs is planned with at least two columns or rows and disposed on the base portions of the first and second gate structures. A second set of contact plugs is planned with at least two columns or rows and disposed on the meander diffusion region. A first conductive layer is disposed on a top end of the first set of contact plugs. A second conductive layer is disposed on a top end of the second set of contact plugs.

An electrode with multiple metallic-layers structure formed by a magnetron sputtering technique for a semiconductor device and method for producing same is disclosed. The ceramic device includes at least one from selected group consisting of ZnO-MOV (metal oxide varistors), BaTiO3-PTC (positive temperature coefficient) thermistors, Mn3O4-NTC (negative temperature coefficient) thermistors, and capacitors. The multiple metallic-layers include a sputtered buffer layer and a sputtered electrical contact layer. The buffer layer includes at least one alloy selected form group consisting of NiCr (Ni from 50-90 wt %), TiNi (Ti from 40-60 wt %), and AlNi (Al from 40-70 wt %) and the thickness of this layer is from greater than zero to less than 100 nm. The electrical contact layer includes at least one of Cu, Ag, Pt, Au, or combination. More specifically, the electrode includes one of NiCr/Cu system, NiCr/Ag system, NiCr/Cu/Ag system, TiNi/Cu/Ag system, or AlNi/Cu/Ag system. The thickness ratio of the electrical contact layer to the intermetallic barrier layer is from 1 to 4.

An electrode with multiple metallic-layers structure formed by a magnetron sputtering technique for a semiconductor device and method for producing same is disclosed. The ceramic device includes at least one from selected group consisting of ZnO-MOV (metal oxide varistors), BaTiO3-PTC (positive temperature coefficient) thermistors, Mn3O4-NTC (negative temperature coefficient) thermistors, and capacitors. The multiple metallic-layers include a sputtered buffer layer and a sputtered electrical contact layer. The buffer layer includes at least one alloy selected form group consisting of NiCr (Ni from 50-90 wt %), TiNi (Ti from 40-60 wt %), and AlNi (Al from 40-70 wt %) and the thickness of this layer is from greater than zero to less than 100 nm. The electrical contact layer includes at least one of Cu, Ag, Pt, Au, or combination. More specifically, the electrode includes one of NiCr/Cu system, NiCr/Ag system, NiCr/Cu/Ag system, TiNi/Cu/Ag system, or AlNi/Cu/Ag system. The thickness ratio of the electrical contact layer to the intermetallic barrier layer is from 1 to 4.

Described herein are switches with asymmetrical anti-series varactor pairs to improve switching performance. The disclosed switches can include asymmetrical varactor pairs to reduce distortions. The asymmetry in the varactor pairs can be associated with geometry of each varactor in the pair. The disclosed switches can stack both symmetrical and asymmetrical varactor pairs. The disclosed switches with asymmetrical anti-series varactor pairs can be configured to improve both H2 and H3 simultaneously.

Described herein are switches with asymmetrical anti-series varactor pairs to improve switching performance. The disclosed switches can include asymmetrical varactor pairs to reduce distortions. The asymmetry in the varactor pairs can be associated with geometry of each varactor in the pair. The disclosed switches can stack both symmetrical and asymmetrical varactor pairs. The disclosed switches with asymmetrical anti-series varactor pairs can be configured to improve both H2 and H3 simultaneously.

A stacked capacitor structure includes a MOS varactor and a stacked capacitor. The stacked capacitor is electrically connected to the MOS varactor. The MOS varactor includes a substrate, a gate, a first source/drain and a second source/drain. The substrate has a well, and the gate is positioned over the well. The first source/drain and the second source/drain are formed in the well and positioned at opposing sides of the gate. The stacked capacitor includes a plurality of metal layers. The metal layers are spaced from each other, stacked above the gate, and positioned below an inductive element.

A stacked capacitor structure includes a MOS varactor and a stacked capacitor. The stacked capacitor is electrically connected to the MOS varactor. The MOS varactor includes a substrate, a gate, a first source/drain and a second source/drain. The substrate has a well, and the gate is positioned over the well. The first source/drain and the second source/drain are formed in the well and positioned at opposing sides of the gate. The stacked capacitor includes a plurality of metal layers. The metal layers are spaced from each other, stacked above the gate, and positioned below an inductive element.