A varactor transistor includes a semiconductor fin having a first conductivity type, a plurality of gate structures separated from each other and surrounding a portion of the semiconductor fin. The plurality of gates structures include a dummy gate structure on an edge of the semiconductor fin, and a first gate structure spaced apart from the dummy gate structure. The dummy gate structure and the gate structure each include a gate insulator layer on a surface portion of the semiconductor fin, a gate on the gate insulator layer, and a spacer on the gate. The varactor transistor also includes a raised source/drain region on the semiconductor fin and between the dummy gate structure and the first gate structure, the raised source/drain region and the gate of the dummy gate structure being electrically connected to a same potential.

A varactor transistor includes a semiconductor fin having a first conductivity type, a plurality of gate structures separated from each other and surrounding a portion of the semiconductor fin. The plurality of gates structures include a dummy gate structure on an edge of the semiconductor fin, and a first gate structure spaced apart from the dummy gate structure. The dummy gate structure and the gate structure each include a gate insulator layer on a surface portion of the semiconductor fin, a gate on the gate insulator layer, and a spacer on the gate. The varactor transistor also includes a raised source/drain region on the semiconductor fin and between the dummy gate structure and the first gate structure, the raised source/drain region and the gate of the dummy gate structure being electrically connected to a same potential.

A gate stack structure for a MOS varactor includes a substrate including a channel region, a high-k dielectric layer on the channel region of the substrate, a P-type work function adjustment layer on the high-k dielectric layer, an N-type work function adjustment layer on the P-type work function adjustment layer, and a metal gate on the N-type work function adjustment layer. The P-type work function adjustment layer includes a first portion and a second portion laterally adjacent to each other, the first portion having a thickness greater than a thickness of the second portion. The gate stack structure in the MOS varactor can increase the tuning range of the MOS varactor.

A gate stack structure for a MOS varactor includes a substrate including a channel region, a high-k dielectric layer on the channel region of the substrate, a P-type work function adjustment layer on the high-k dielectric layer, an N-type work function adjustment layer on the P-type work function adjustment layer, and a metal gate on the N-type work function adjustment layer. The P-type work function adjustment layer includes a first portion and a second portion laterally adjacent to each other, the first portion having a thickness greater than a thickness of the second portion. The gate stack structure in the MOS varactor can increase the tuning range of the MOS varactor.

Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.

Embodiments are provided herein for low loss coupling capacitor structures. The embodiments include a n-type varactor (NVAR) configuration and p-type varactor (PVAR) configuration. The structure in the NVAR configuration comprises a p-doped semiconductor substrate (Psub), a deep n-doped semiconductor well (DNW) in the Psub, and a p-doped semiconductor well (P well) in the DNW. The circuit structure further comprises a source terminal of a p-doped semiconductor material within P well, and a drain terminal of the p-doped semiconductor material within the P well. Additionally, the circuit structure comprises an insulated gate on the surface of the P well, a metal pattern comprising a plurality of layers of metal lines, and a plurality of vias through the metal lines. The vias are contacts connecting the metal lines to the gate, the source terminal, and the drain terminal.

An electrical device includes at least one graphene quantum capacitance varactor. In some examples, the graphene quantum capacitance varactor includes an insulator layer, a graphene layer disposed on the insulator layer, a dielectric layer disposed on the graphene layer, a gate electrode formed on the dielectric layer, and at least one contact electrode disposed on the graphene layer and making electrical contact with the graphene layer. In other examples, the graphene quantum capacitance varactor includes an insulator layer, a gate electrode recessed in the insulator layer, a dielectric layer formed on the gate electrode, a graphene layer formed on the dielectric layer, wherein the graphene layer comprises an exposed surface opposite the dielectric layer, and at least one contact electrode formed on the graphene layer and making electrical contact with the graphene layer.

An electrical device includes at least one graphene quantum capacitance varactor. In some examples, the graphene quantum capacitance varactor includes an insulator layer, a graphene layer disposed on the insulator layer, a dielectric layer disposed on the graphene layer, a gate electrode formed on the dielectric layer, and at least one contact electrode disposed on the graphene layer and making electrical contact with the graphene layer. In other examples, the graphene quantum capacitance varactor includes an insulator layer, a gate electrode recessed in the insulator layer, a dielectric layer formed on the gate electrode, a graphene layer formed on the dielectric layer, wherein the graphene layer comprises an exposed surface opposite the dielectric layer, and at least one contact electrode formed on the graphene layer and making electrical contact with the graphene layer.

FinFET varactors having low threshold voltages and methods of making the same are disclosed herein. An exemplary FinFET varactor includes a fin and a gate structure disposed over a portion of the fin, such that the gate structure is disposed between a first source/drain feature and a second source/drain feature that include a first type dopant. The portion of the fin includes the first type dopant and a second type dopant. A dopant concentration of the first type dopant and a dopant concentration of the second type dopant vary from an interface between the fin and the gate structure to a first depth in the fin. The dopant concentration of the first type dopant is greater than the dopant concentration of the second type dopant from a second depth to a third depth in the fin, where the second depth and the third depth are less than the first depth.

FinFET varactors having low threshold voltages and methods of making the same are disclosed herein. An exemplary FinFET varactor includes a fin and a gate structure disposed over a portion of the fin, such that the gate structure is disposed between a first source/drain feature and a second source/drain feature that include a first type dopant. The portion of the fin includes the first type dopant and a second type dopant. A dopant concentration of the first type dopant and a dopant concentration of the second type dopant vary from an interface between the fin and the gate structure to a first depth in the fin. The dopant concentration of the first type dopant is greater than the dopant concentration of the second type dopant from a second depth to a third depth in the fin, where the second depth and the third depth are less than the first depth.