Patent classifications
H01L2924/01059
Integrated circuit chip, method of manufacturing the integrated circuit chip, and integrated circuit package and display apparatus including the integrated circuit chip
An integrated circuit (IC) chip includes a via contact plug extending inside a through hole passing through a substrate and a device layer, a via contact liner surrounding the via contact plug, a connection pad liner extending along a bottom surface of the substrate, a dummy bump structure integrally connected to the via contact plug, and a bump structure connected to the connection pad liner. A method of manufacturing an IC chip includes forming an under bump metallurgy (UBM) layer inside and outside the through hole and forming a first connection metal layer, a second connection metal layer, and a third connection metal layer. The first connection metal layer covers the UBM layer inside the through hole, the second connection metal layer is integrally connected to the first connection metal layer, and the third connection metal layer covers the UBM layer on the connection pad liner.
Integrated circuit chip, method of manufacturing the integrated circuit chip, and integrated circuit package and display apparatus including the integrated circuit chip
An integrated circuit (IC) chip includes a via contact plug extending inside a through hole passing through a substrate and a device layer, a via contact liner surrounding the via contact plug, a connection pad liner extending along a bottom surface of the substrate, a dummy bump structure integrally connected to the via contact plug, and a bump structure connected to the connection pad liner. A method of manufacturing an IC chip includes forming an under bump metallurgy (UBM) layer inside and outside the through hole and forming a first connection metal layer, a second connection metal layer, and a third connection metal layer. The first connection metal layer covers the UBM layer inside the through hole, the second connection metal layer is integrally connected to the first connection metal layer, and the third connection metal layer covers the UBM layer on the connection pad liner.
Methods and Apparatus for Measuring Analytes Using Large Scale FET Arrays
Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.
AL BONDING WIRE
There is provided an Al bonding wire which can achieve a sufficient bonding reliability of bonded parts of the bonding wire under a high temperature state where a semiconductor device using the Al bonding wire is operated. The Al bonding wire contains 0.01 to 1% of Sc, and further contains 0.01 to 0.1% in total of at least one or more of Y, La, Ce, Pr and Nd. With regard to the Al bonding wire, a recrystallization temperature thereof is increased, so that the proceeding of recrystallization of the bonding wire can be suppressed, and strength of the wire can be prevented from being decreased even when the semiconductor device is continuously used under a high temperature environment. Accordingly, the Al bonding wire can sufficiently secure the reliability of the bonded parts after a high-temperature long-term hysteresis.
AL BONDING WIRE
There is provided an Al bonding wire which can achieve a sufficient bonding reliability of bonded parts of the bonding wire under a high temperature state where a semiconductor device using the Al bonding wire is operated. The Al bonding wire contains 0.01 to 1% of Sc, and further contains 0.01 to 0.1% in total of at least one or more of Y, La, Ce, Pr and Nd. With regard to the Al bonding wire, a recrystallization temperature thereof is increased, so that the proceeding of recrystallization of the bonding wire can be suppressed, and strength of the wire can be prevented from being decreased even when the semiconductor device is continuously used under a high temperature environment. Accordingly, the Al bonding wire can sufficiently secure the reliability of the bonded parts after a high-temperature long-term hysteresis.
3D IC method and device
A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.
Method for fabricating electronic device package
The invention provides an electronic device package and fabrication method thereof. The electronic device package includes a sensor chip. An upper surface of the sensor chip comprises a sensing film. A covering plate having an opening structure covers the upper surface of the sensor chip. A cavity is between the covering plate and the sensor chip, corresponding to a position of the sensing film, where the cavity communicates with the opening structure. A spacer is between the covering plate and the sensor chip, surrounding the cavity. A pressure releasing region is between the spacer and the sensing film.
Methods and apparatus for measuring analytes using large scale FET arrays
Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.
Methods and apparatus for measuring analytes using large scale FET arrays
Methods and apparatus relating to very large scale FET arrays for analyte measurements. ChemFET (e.g., ISFET) arrays may be fabricated using conventional CMOS processing techniques based on improved FET pixel and array designs that increase measurement sensitivity and accuracy, and at the same time facilitate significantly small pixel sizes and dense arrays. Improved array control techniques provide for rapid data acquisition from large and dense arrays. Such arrays may be employed to detect a presence and/or concentration changes of various analyte types in a wide variety of chemical and/or biological processes. In one example, chemFET arrays facilitate DNA sequencing techniques based on monitoring changes in hydrogen ion concentration (pH), changes in other analyte concentration, and/or binding events associated with chemical processes relating to DNA synthesis.
3D IC method and device
A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.