A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive structure comprising a first portion overlying the base structure and second portions vertically extending from the first portion and into the base structure, a stack structure overlying the doped semiconductive structure, cell pillar structures vertically extending through the stack structure and to the doped semiconductive structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The carrier structure and the second portions of the doped semiconductive structure are removed. The first portion of the doped semiconductive structure is then patterned to form at least one source structure coupled to the cell pillar structures. Devices and systems are also described.

A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive structure comprising a first portion overlying the base structure and second portions vertically extending from the first portion and into the base structure, a stack structure overlying the doped semiconductive structure, cell pillar structures vertically extending through the stack structure and to the doped semiconductive structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The carrier structure and the second portions of the doped semiconductive structure are removed. The first portion of the doped semiconductive structure is then patterned to form at least one source structure coupled to the cell pillar structures. Devices and systems are also described.

A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive material overlying the base structure, a stack structure overlying the doped semiconductive material, cell pillar structures vertically extending through the stack structure and the doped semiconductive material and into the base structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The base structure and portions of the cell pillar structures vertically extending into the base structure are removed to expose the doped semiconductive material. The doped semiconductive material is then patterned to form at least one source structure over the stack structure and coupled to the cell pillar structures. Microelectronic devices and electronic systems are also described.

A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive material overlying the base structure, a stack structure overlying the doped semiconductive material, cell pillar structures vertically extending through the stack structure and the doped semiconductive material and into the base structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The base structure and portions of the cell pillar structures vertically extending into the base structure are removed to expose the doped semiconductive material. The doped semiconductive material is then patterned to form at least one source structure over the stack structure and coupled to the cell pillar structures. Microelectronic devices and electronic systems are also described.

Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

Embodiments of the present disclosure are directed towards techniques and configurations for layered interconnect structures for bridge interconnection in integrated circuit assemblies. In one embodiment, an apparatus may include a substrate and a bridge embedded in the substrate. The bridge may be configured to route electrical signals between two dies. An interconnect structure, electrically coupled with the bridge, may include a via structure including a first conductive material, a barrier layer including a second conductive material disposed on the via structure, and a solderable material including a third conductive material disposed on the barrier layer. The first conductive material, the second conductive material, and the third conductive material may have different chemical composition. Other embodiments may be described and/or claimed.

A redistribution layer for an integrated circuit is made by forming a conductive interconnection layer; forming a conductive body in electrical contract with the interconnection layer; and covering the conductive body with a first coating layer having a thickness less than 100 nm. The first coating layer is configured to provide a protection against oxidation and/or corrosion of the conductive body. To carry out an electrical test of the integrated circuit, a testing probe locally perforates the first coating layer until the conductive body is electrically contacted by the testing probe.

A method for forming a packaged electronic device includes providing a substrate having a first major surface and an opposing second major surface. The method includes attaching an electronic device to the first major surface of the substrate and providing a first conductive structure coupled to at least a first portion of the substrate. The method includes forming a dielectric layer overlying at least part of the first conductive structure. The method includes forming a conductive layer overlying the dielectric layer and connected to a second portion of the substrate. The first conductive structure, the dielectric layer, and conductive layer are configured as a capacitor structure and further configured as one or more of an enclosure structure or a stiffener structure for the packaged electronic device.

A method for forming a packaged electronic device includes providing a substrate having a first major surface and an opposing second major surface. The method includes attaching an electronic device to the first major surface of the substrate and providing a first conductive structure coupled to at least a first portion of the substrate. The method includes forming a dielectric layer overlying at least part of the first conductive structure. The method includes forming a conductive layer overlying the dielectric layer and connected to a second portion of the substrate. The first conductive structure, the dielectric layer, and conductive layer are configured as a capacitor structure and further configured as one or more of an enclosure structure or a stiffener structure for the packaged electronic device.

Disclosed is a method for manufacturing a flip chip, in which a gold typically used in a flip chip manufacturing is adhered by conductive adhesives, wherein the method comprises steps of depositing a metal seed layer on a substrate; applying and patterning a photoresist or a dry film; forming a gold bump by electroplating; patterning the seed layer; forming an insulating layer on the seed layer and upper end of the gold bump; and patterning an insulating layer. Accordingly, it is possible to manufacture a flip chip, in which electrical function between bumps can be evaluated, with less cost.