Patent classifications
H01L2924/0449
INTEGRATED CIRCUIT AND PREPARATION METHOD THEREOF, THREE-DIMENSIONAL INTEGRATED CIRCUIT, AND ELECTRONIC DEVICE
An integrated circuit includes a substrate, an electronic component, a wiring layer, a dielectric bonding layer, a connection pattern, and a barrier layer. The wiring layer is disposed on the substrate, and is electrically connected to the electronic component. The wiring layer includes a metal trace. The dielectric bonding layer is disposed on a side that is of the wiring layer and that is away from the substrate. The connection pattern runs through the dielectric bonding layer, and is electrically connected to the metal trace. The connection pattern includes a seed layer and a conductive block that are stacked, and the seed layer is located on a side that is of the conductive block and that is close to the substrate. The barrier layer is disposed between the conductive block and the dielectric bonding layer, and surrounds a side surface of the conductive block.