This silver paste is used to form a silver paste layer by applying the silver paste directly on the surface of a copper or copper alloy member, and the silver paste includes a silver powder, a fatty acid silver salt, an aliphatic amine, a high-dielectric-constant alcohol having a dielectric constant of 30 or more, and a solvent having a dielectric constant of less than 30. The content of the high-dielectric-constant alcohol is preferably 0.01% by mass to 5% by mass when an amount of the silver paste is taken as 100% by mass.

This silver paste is used to form a silver paste layer by applying the silver paste directly on the surface of a copper or copper alloy member, and the silver paste includes a silver powder, a fatty acid silver salt, an aliphatic amine, a high-dielectric-constant alcohol having a dielectric constant of 30 or more, and a solvent having a dielectric constant of less than 30. The content of the high-dielectric-constant alcohol is preferably 0.01% by mass to 5% by mass when an amount of the silver paste is taken as 100% by mass.

An underfill film for semiconductor packages and a method for manufacturing a semiconductor package using the underfill film are disclosed. The underfill film includes an adhesive layer in which a melt viscosity and an onset temperature are adjusted to a predetermined range such that production efficiency may be improved by simplifying packaging process of the semiconductor packages. Also the underfill film and the manufacturing process may improve connection reliability of the package.

An underfill film for semiconductor packages and a method for manufacturing a semiconductor package using the underfill film are disclosed. The underfill film includes an adhesive layer in which a melt viscosity and an onset temperature are adjusted to a predetermined range such that production efficiency may be improved by simplifying packaging process of the semiconductor packages. Also the underfill film and the manufacturing process may improve connection reliability of the package.

A method for evaluating pickup property of a dicing/die-bonding integrated film including a base layer, an adhesive, and a bonding adhesive layer in order, the method including preparing a laminate including the dicing/die-bonding integrated film and a wafer having a thickness of 10 to 100 μm laminated on the bonding adhesive layer, singulating the wafer into a plurality of chips having an area of 9 mm.sup.2 or less, pushing a center portion of the chip from a side of the base layer, and measuring a peeling strength when an edge of the chip is peeled off from the adhesive layer.

A method for evaluating pickup property of a dicing/die-bonding integrated film including a base layer, an adhesive, and a bonding adhesive layer in order, the method including preparing a laminate including the dicing/die-bonding integrated film and a wafer having a thickness of 10 to 100 μm laminated on the bonding adhesive layer, singulating the wafer into a plurality of chips having an area of 9 mm.sup.2 or less, pushing a center portion of the chip from a side of the base layer, and measuring a peeling strength when an edge of the chip is peeled off from the adhesive layer.

A die stack structure includes an interconnection structure, a logic die, a control die, a first insulating encapsulant, a dummy die, a memory cube and a second insulating encapsulant. The logic die is electrically connected to the interconnection structure. The logic die comprises a first dielectric bonding structure. The control die is laterally separated from the logic die and electrically connected to the interconnection structure. The first insulating encapsulant laterally encapsulates the logic die and the control die. The dummy die is stacked on the logic die, the logic die is located between the interconnection structure and the dummy die, the dummy die comprises a second dielectric bonding structure, and a bonding interface is located between the first dielectric bonding structure and the second dielectric bonding structure. The memory cube is stacked on and electrically connected to the control die, wherein the control die is located between the interconnection structure and the memory cube. The second insulating encapsulant laterally encapsulates the dummy die and the memory cube.

A die stack structure includes an interconnection structure, a logic die, a control die, a first insulating encapsulant, a dummy die, a memory cube and a second insulating encapsulant. The logic die is electrically connected to the interconnection structure. The logic die comprises a first dielectric bonding structure. The control die is laterally separated from the logic die and electrically connected to the interconnection structure. The first insulating encapsulant laterally encapsulates the logic die and the control die. The dummy die is stacked on the logic die, the logic die is located between the interconnection structure and the dummy die, the dummy die comprises a second dielectric bonding structure, and a bonding interface is located between the first dielectric bonding structure and the second dielectric bonding structure. The memory cube is stacked on and electrically connected to the control die, wherein the control die is located between the interconnection structure and the memory cube. The second insulating encapsulant laterally encapsulates the dummy die and the memory cube.

A die stack structure includes an interconnection structure, a logic die, a control die, a first insulating encapsulant, a dummy die, a memory cube and a second insulating encapsulant. The logic die is electrically connected to the interconnection structure. The logic die comprises a first dielectric bonding structure. The control die is laterally separated from the logic die and electrically connected to the interconnection structure. The first insulating encapsulant laterally encapsulates the logic die and the control die. The dummy die is stacked on the logic die, the logic die is located between the interconnection structure and the dummy die, the dummy die comprises a second dielectric bonding structure, and a bonding interface is located between the first dielectric bonding structure and the second dielectric bonding structure. The memory cube is stacked on and electrically connected to the control die, wherein the control die is located between the interconnection structure and the memory cube. The second insulating encapsulant laterally encapsulates the dummy die and the memory cube.

A die stack structure includes an interconnection structure, a logic die, a control die, a first insulating encapsulant, a dummy die, a memory cube and a second insulating encapsulant. The logic die is electrically connected to the interconnection structure. The logic die comprises a first dielectric bonding structure. The control die is laterally separated from the logic die and electrically connected to the interconnection structure. The first insulating encapsulant laterally encapsulates the logic die and the control die. The dummy die is stacked on the logic die, the logic die is located between the interconnection structure and the dummy die, the dummy die comprises a second dielectric bonding structure, and a bonding interface is located between the first dielectric bonding structure and the second dielectric bonding structure. The memory cube is stacked on and electrically connected to the control die, wherein the control die is located between the interconnection structure and the memory cube. The second insulating encapsulant laterally encapsulates the dummy die and the memory cube.