A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.

A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.

An integrated circuit device includes a wiring structure, first and second inter-wiring insulating layers, redistributions patterns and a cover insulating layer. The wiring structure includes wiring layers having a multilayer wiring structure and via plugs. The first inter-wiring insulating layer that surrounds the wiring structure on a substrate. The second inter-wiring insulating layer is on the first inter-wiring insulating layer, and redistribution via plugs are connected to the wiring structure through the second inter-wiring insulating layer. The redistribution patterns includes pad patterns and dummy patterns on the second inter-wiring insulating layer. Each patterns has a thickness greater than a thickness of each wiring layer. The cover insulating layer covers some of the redistribution patterns. The dummy patterns are in the form of lines that extend in a horizontal direction parallel to the substrate.

An integrated circuit device includes a wiring structure, first and second inter-wiring insulating layers, redistributions patterns and a cover insulating layer. The wiring structure includes wiring layers having a multilayer wiring structure and via plugs. The first inter-wiring insulating layer that surrounds the wiring structure on a substrate. The second inter-wiring insulating layer is on the first inter-wiring insulating layer, and redistribution via plugs are connected to the wiring structure through the second inter-wiring insulating layer. The redistribution patterns includes pad patterns and dummy patterns on the second inter-wiring insulating layer. Each patterns has a thickness greater than a thickness of each wiring layer. The cover insulating layer covers some of the redistribution patterns. The dummy patterns are in the form of lines that extend in a horizontal direction parallel to the substrate.

Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having an annular PSPI region formed under a BLM pad. An annular region is formed under a barrier layer metallurgy (BLM) pad. The annular region includes a photosensitive polyimide (PSPI). A conductive pedestal is formed on a surface of the BLM pad and a solder bump is formed on a surface of the conductive pedestal. The annular PSPI region reduces wafer warpage and ULK peeling stress.

Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having an annular PSPI region formed under a BLM pad. An annular region is formed under a barrier layer metallurgy (BLM) pad. The annular region includes a photosensitive polyimide (PSPI). A conductive pedestal is formed on a surface of the BLM pad and a solder bump is formed on a surface of the conductive pedestal. The annular PSPI region reduces wafer warpage and ULK peeling stress.

A light emitting device package according to an embodiment may include a first package body including first and second openings passing through the upper surface and lower surface thereof; a second package body disposed on the first package body and including a third opening passing through the upper surface and lower surface thereof; a light emitting device disposed in the third opening; a first resin disposed between the upper surface of the first package body and the light emitting device; and a second resin disposed in the third opening. According to the embodiment, the upper surface of the first package body may be coupled to the lower surface of the second package body, the first package body may include a recess recessed from the upper surface of the first package body to the lower surface of the first package body, the first resin may be disposed in the recess, the first resin and the second resin include materials different from each other, and the first resin may be in contact with the light emitting device and the second resin.

A light emitting device package according to an embodiment may include a first package body including first and second openings passing through the upper surface and lower surface thereof; a second package body disposed on the first package body and including a third opening passing through the upper surface and lower surface thereof; a light emitting device disposed in the third opening; a first resin disposed between the upper surface of the first package body and the light emitting device; and a second resin disposed in the third opening. According to the embodiment, the upper surface of the first package body may be coupled to the lower surface of the second package body, the first package body may include a recess recessed from the upper surface of the first package body to the lower surface of the first package body, the first resin may be disposed in the recess, the first resin and the second resin include materials different from each other, and the first resin may be in contact with the light emitting device and the second resin.

A package structure includes a semiconductor die and a redistribution circuit structure. The redistribution circuit structure is disposed on and electrically connected to the semiconductor die and includes a patterned conductive layer, a dielectric layer, and an inter-layer film. The dielectric layer is disposed on the patterned conductive layer. The inter-layer film is sandwiched between the dielectric layer and the patterned conductive layer, and the patterned conductive layer is separated from the dielectric layer through the inter-layer film.

A semiconductor chip includes a device layer on a substrate, the device layer including a plurality of semiconductor devices; a wiring structure and a lower inter-wiring dielectric layer each on the device layer, the lower inter-wiring dielectric layer surrounding the wiring structure and having a lower permittivity than silicon oxide; an upper inter-wiring dielectric layer arranged on the lower inter-wiring dielectric layer; an isolation recess arranged along an edge of the substrate, the isolation recess formed on side surfaces of the lower and upper inter-wiring dielectric layers and having a bottom surface at a level equal to or lower than that of a bottom surface of the lower inter-wiring dielectric layer; and a cover dielectric layer covering the side surfaces of the lower and upper inter-wiring dielectric layers and the bottom surface of the isolation recess.