A method of forming a semiconductor package is provided. The method includes forming a metallization stack over a semiconductor die. Polymer particles are mounted over the metallization stack. Each of the polymer particles is coated with a first bonding layer. A heat spreader lid is bonded with the semiconductor die by reflowing the first bonding layer. A composite thermal interface material (TIM) structure is formed between the heat spreader lid and the semiconductor die during the bonding. The composite TIM structure includes the first bonding layer and the polymer particles embedded in the first bonding layer.

A method of forming a semiconductor package is provided. The method includes forming a metallization stack over a semiconductor die. Polymer particles are mounted over the metallization stack. Each of the polymer particles is coated with a first bonding layer. A heat spreader lid is bonded with the semiconductor die by reflowing the first bonding layer. A composite thermal interface material (TIM) structure is formed between the heat spreader lid and the semiconductor die during the bonding. The composite TIM structure includes the first bonding layer and the polymer particles embedded in the first bonding layer.

In a described example, an apparatus includes: a patch antenna formed in a first conductor layer on a device side surface of a multilayer package substrate, the multilayer package substrate including conductor layers spaced from one another by dielectric material and coupled to one another by conductive vertical connection layers, the multilayer package substrate having a board side surface opposite the device side surface; and a semiconductor die mounted to the device side surface of the multilayer package substrate spaced from and coupled to the patch antenna.

In a described example, an apparatus includes: a patch antenna formed in a first conductor layer on a device side surface of a multilayer package substrate, the multilayer package substrate including conductor layers spaced from one another by dielectric material and coupled to one another by conductive vertical connection layers, the multilayer package substrate having a board side surface opposite the device side surface; and a semiconductor die mounted to the device side surface of the multilayer package substrate spaced from and coupled to the patch antenna.

A semiconductor package includes: a first package substrate; a first semiconductor device mounted on the first package substrate; a second package substrate arranged on an upper part of the first semiconductor device; and a heat-dissipating material layer arranged between the first semiconductor device and the second package substrate and having a thermal conductivity of approximately 0.5 W/m.Math.K to approximately 20 W/m.Math.K, wherein the heat-dissipating material layer is in direct contact with an upper surface of the first semiconductor device and a conductor of the second package substrate.

A semiconductor package includes: a first package substrate; a first semiconductor device mounted on the first package substrate; a second package substrate arranged on an upper part of the first semiconductor device; and a heat-dissipating material layer arranged between the first semiconductor device and the second package substrate and having a thermal conductivity of approximately 0.5 W/m.Math.K to approximately 20 W/m.Math.K, wherein the heat-dissipating material layer is in direct contact with an upper surface of the first semiconductor device and a conductor of the second package substrate.

Disclosed is a method for manufacturing a semiconductor device which includes: a semiconductor chip; a substrate and/or another semiconductor chip; and an adhesive layer interposed therebetween. This method comprises the steps of: heating and pressuring a laminate having: the semiconductor chip; the substrate; the another semiconductor chip or a semiconductor wafer; and the adhesive layer by interposing the laminate with pressing members for temporary press-bonding to thereby temporarily press-bond the substrate and the another semiconductor chip or the semiconductor wafer to the semiconductor chip; and heating and pressuring the laminate by interposing the laminate with pressing members for main press-bonding, which are separately prepared from the pressing members for temporary press-bonding, to thereby electrically connect a connection portion of the semiconductor chip and a connection portion of the substrate or the another semiconductor chip.

Disclosed is a method for manufacturing a semiconductor device which includes: a semiconductor chip; a substrate and/or another semiconductor chip; and an adhesive layer interposed therebetween. This method comprises the steps of: heating and pressuring a laminate having: the semiconductor chip; the substrate; the another semiconductor chip or a semiconductor wafer; and the adhesive layer by interposing the laminate with pressing members for temporary press-bonding to thereby temporarily press-bond the substrate and the another semiconductor chip or the semiconductor wafer to the semiconductor chip; and heating and pressuring the laminate by interposing the laminate with pressing members for main press-bonding, which are separately prepared from the pressing members for temporary press-bonding, to thereby electrically connect a connection portion of the semiconductor chip and a connection portion of the substrate or the another semiconductor chip.

A semiconductor device according to an embodiment includes a lead frame, a semiconductor chip provided above the lead frame, and a bonding material including a sintered material containing a predetermined metal material and a predetermined resin, where the bonding material includes a first portion provided between the lead frame and the semiconductor chip, and a second portion provided on the lead frame around the semiconductor chip, where the bonding material bonds the lead frame and the semiconductor chip, wherein an angle formed by a lower face of the semiconductor chip and an upper face of the second portion adjacent to the lower face is 80 degrees or less.

A semiconductor device according to an embodiment includes a lead frame, a semiconductor chip provided above the lead frame, and a bonding material including a sintered material containing a predetermined metal material and a predetermined resin, where the bonding material includes a first portion provided between the lead frame and the semiconductor chip, and a second portion provided on the lead frame around the semiconductor chip, where the bonding material bonds the lead frame and the semiconductor chip, wherein an angle formed by a lower face of the semiconductor chip and an upper face of the second portion adjacent to the lower face is 80 degrees or less.