An apparatus comprising: a module; a substrate; and electrolyte between the module and the substrate, wherein an electronic component is formed between the module and the substrate and wherein the electrolyte is configured to function as the electrolyte in the electronic component and also as the adhesive to attach the module to the substrate.

A dicing die attach film including a dicing film and a die attach film laminated on the dicing film, in which the die attach film has an arithmetic average roughness Ra1 of from 0.05 to 2.50 μm at a surface in contact with the dicing film, and a value of ratio of Ra1 to an arithmetic average roughness Ra2 at a surface that is of the die attach film and is opposite to the surface in contact with the dicing film is from 1.05 to 28.00.

A dicing die attach film including a dicing film and a die attach film laminated on the dicing film, in which the die attach film has an arithmetic average roughness Ra1 of from 0.05 to 2.50 μm at a surface in contact with the dicing film, and a value of ratio of Ra1 to an arithmetic average roughness Ra2 at a surface that is of the die attach film and is opposite to the surface in contact with the dicing film is from 1.05 to 28.00.

A thermosetting sheet according to the present invention includes a thermosetting resin and a thermoplastic resin, in which a thickness change rate when a temperature is changed from 25° C. to 200° C. is 0% or more and 10% or less.

A thermosetting sheet according to the present invention includes a thermosetting resin and a thermoplastic resin, in which a thickness change rate when a temperature is changed from 25° C. to 200° C. is 0% or more and 10% or less.

A semiconductor package manufacturing method of the disclosure includes providing a multilayer adhesive film, forming a notch and a plurality of openings extending through the multilayer adhesive film, attaching the multilayer adhesive film to a back side of a wafer to form a stack, separating the stack into a plurality of individual stacks, separating each of the plurality of individual stacks into an upper stack and a lower stack, providing a substrate on which a first semiconductor chip is mounted, and stacking the upper stack on the first semiconductor chip. The upper stack includes a second semiconductor chip and a die attach pattern covering a portion of a back surface of the second semiconductor chip. A first side surface of the die attach pattern is aligned with a first side surface of the first semiconductor chip.

A semiconductor package manufacturing method of the disclosure includes providing a multilayer adhesive film, forming a notch and a plurality of openings extending through the multilayer adhesive film, attaching the multilayer adhesive film to a back side of a wafer to form a stack, separating the stack into a plurality of individual stacks, separating each of the plurality of individual stacks into an upper stack and a lower stack, providing a substrate on which a first semiconductor chip is mounted, and stacking the upper stack on the first semiconductor chip. The upper stack includes a second semiconductor chip and a die attach pattern covering a portion of a back surface of the second semiconductor chip. A first side surface of the die attach pattern is aligned with a first side surface of the first semiconductor chip.

A dicing die bonding film according to the present invention includes: a dicing tape including a base layer and an adhesive layer laminated on the base layer; and a die bonding layer laminated on the adhesive layer of the deicing tape; the die bonding layer including a matrix resin, a thiol-group-containing compound, and conductive particles.

A dicing die bonding film according to the present invention includes: a dicing tape including a base layer and an adhesive layer laminated on the base layer; and a die bonding layer laminated on the adhesive layer of the deicing tape; the die bonding layer including a matrix resin, a thiol-group-containing compound, and conductive particles.

A lead-free solder alloy includes 2.0% by mass or more and 4.0% by mass or less of Ag, 0.3% by mass or more and 0.7% by mass or less of Cu, 1.2% by mass or more and 2.0% by mass or less of Bi, 0.5% by mass or more and 2.1% by mass or less of In, 3.0% by mass or more and 4.0% by mass or less of Sb, 0.001% by mass or more and 0.05% by mass or less of Ni, 0.001% by mass or more and 0.01% by mass or less of Co, and the balance being Sn.