Patent classifications
H01L2924/096
PACKAGE WITH PAD HAVING OPEN NOTCH
A package is disclosed. In one example, the package comprises an electronic component having a first main surface with an electrically conductive first pad. The first pad has an open notch, and a spacer body mounted on the first pad and bridging at least part of the open notch.
PACKAGE WITH PAD HAVING OPEN NOTCH
A package is disclosed. In one example, the package comprises an electronic component having a first main surface with an electrically conductive first pad. The first pad has an open notch, and a spacer body mounted on the first pad and bridging at least part of the open notch.
CARRIER WITH EMBEDDED ELECTRICAL CONNECTION, COMPONENT AND METHOD FOR PRODUCING A CARRIER
In an embodiment a carrier includes a shaped body, a lead frame, a first electrode and a second electrode, wherein the first electrode includes a first subregion of the lead frame, a second subregion of the lead frame, and an electrical connection connecting the first subregion to the second subregion, wherein the first subregion is laterally spaced from the second subregion by an intermediate region, wherein the lead frame has at least one subsection, which is located at least in places in the intermediate region and thus in a lateral direction between the first subregion and the second subregion of the first electrode, wherein the intermediate region is at least partially filled by the shaped body or directly adjoins the shaped body, the electrical connection being embedded in the shaped body, and wherein the subsection of the lead frame is neither a subregion of the first electrode nor a subregion of the second electrode.
PACKAGE STRUCTURE
A package structure is provided. The package structure includes a lower substrate, an upper substrate, and a chip. The lower substrate defines a lower through hole. The upper substrate is over the lower substrate and defines an upper through hole connected to the lower through hole. A portion of a top surface of the lower substrate is exposed by the upper through hole. The chip is at least partially accommodated by the upper through hole and supported by the portion of the top surface of the lower substrate.