A semiconductor chip includes a front surface and a back surface, a source pad, a drain pad and a gate pad on the front surface; a die pad under the semiconductor chip and bonded to the semiconductor chip; a source lead, electrically connected to the die pad; a drain lead and a gate lead, disposed on a periphery of the die pad; and a sealing resin. A plurality of vias for external connection are formed to connect to the source pad. A first subset of the plurality of vias for external connection is disposed along a first side of the source pad, and a second subset of the plurality of vias for external connection is disposed along a second side of the source pad, wherein the first and second sides are arranged adjacent to each other to form a first edge of the source pad.

A III-nitride-based semiconductor packaged structure includes a lead frame, an adhesive layer, a III-nitride-based die, an encapsulant, and at least one bonding wire. The lead frame includes a die paddle and a lead. The die paddle has first and second recesses arranged in a top surface of the die paddle. The first recesses are located adjacent to a relatively central region of the top surface. The second recesses are located adjacent to a relatively peripheral region of the top surface. The first recess has a shape different from the second recess from a top-view perspective. The adhesive layer is disposed on the die paddle to fill into the first recesses. The III-nitride-based die is disposed on the adhesive layer. The encapsulant encapsulates the lead frame and the III-nitride-based die. The second recesses are filled with the encapsulant. The bonding wire is encapsulated by the encapsulant.

The present invention provides a semiconductor device for reducing parasitic inductance. The semiconductor device of the present invention includes: a semiconductor chip, including a front surface and a hack surface, and including a source pad, a drain pad and a gate pad on the front surface; a die pad, disposed under the semiconductor chip and bonded to the hack surface of the semiconductor chip; a source lead, electrically connected to the die pad; a drain lead and a gate lead, disposed on a periphery of the die pad; and a sealing resin, sealing the semiconductor chip, the die pad and each of the leads. At least one via for external connection is formed in the semiconductor chip to connect to the source pad, and the via for external connection is disposed on a circumferential portion of the semiconductor chip in perspective view.

This invention relates to a method for bonding of a first contact surface of a first substrate to a second contact surface of a second substrate with the following steps, especially the following sequence: forming a first reservoir in a surface layer on the first contact surface and a second reservoir in a surface layer on the second contact surface, the surface layers of the first and second contact surfaces being comprised of respective native oxide materials of one or more second educts respectively contained in reaction layers of the first and second substrates, partially filling the first and second reservoirs with one or more first educts; and reacting the first educts filled in the first reservoir with the second educts contained in the reaction layer of the second substrate to at least partially strengthen a permanent bond formed between the first and second contact surfaces.

A package includes a semiconductor die forming a power field effect transistor (FET), a control die, and a first leadframe. The control die is arranged on a first surface of the first leadframe, and the semiconductor die is arranged on an opposing second surface of the first leadframe. The package further includes a second leadframe including a first surface and a second surface opposing the first surface, wherein the semiconductor die is arranged on the first surface of the second leadframe to facilitate heat transfer therethrough. The package also includes mold compound at least partially covering the semiconductor die, the control die, the first leadframe and the second leadframe with the second surface of the second leadframe exposed.

A package includes a semiconductor die forming a power field effect transistor (FET), a control die, and a first leadframe. The control die is arranged on a first surface of the first leadframe, and the semiconductor die is arranged on an opposing second surface of the first leadframe. The package further includes a second leadframe including a first surface and a second surface opposing the first surface, wherein the semiconductor die is arranged on the first surface of the second leadframe to facilitate heat transfer therethrough. The package also includes mold compound at least partially covering the semiconductor die, the control die, the first leadframe and the second leadframe with the second surface of the second leadframe exposed.

The present invention provides a semiconductor device for reducing parasitic inductance.

The semiconductor device of the present invention includes: a semiconductor chip, including a front surface and a hack surface, and including a source pad. a drain pad and a gate pad on the front surface; a die pad, disposed under the semiconductor chip and bonded to the hack surface of the semiconductor chip; a source lead, electrically connected to the die pad; a drain lead and a gate lead, disposed on a periphery of the die pad; and a sealing resin, sealing the semiconductor chip, the die pad and each of the leads. At least one via for external connection is formed in the semiconductor chip to connect to the source pad, and the via for external connection is disposed on a circumferential portion of the semiconductor chip in perspective view.

This invention relates to a method for bonding of a first contact surface of a first substrate to a second contact surface of a second substrate with the following steps, especially the following sequence: forming a reservoir in a surface layer on the first contact surface, the first surface layer consisting at least largely of a native oxide material, at least partial filling of the reservoir with a first educt or a first group of educts, the first contact surface making contact with the second contact surface for formation of a prebond connection, forming a permanent bond between the first and second contact surface, at least partially strengthened by the reaction of the first educt with a second educt contained in a reaction layer of the second substrate.

A method for applying a bonding layer that is comprised of a basic layer and a protective layer on a substrate with the following method steps: application of an oxidizable basic material as a basic layer on a bonding side of the substrate, at least partial covering of the basic layer with a protective material that is at least partially dissolvable in the basic material as a protective layer. In addition, the invention relates to a corresponding substrate.

A III-nitride-based semiconductor packaged structure includes a lead frame, an adhesive layer, a III-nitride-based die, an encapsulant, and at least one bonding wire. The lead frame includes a die paddle and a lead. The die paddle has first and second recesses arranged in a top surface of the die paddle. The first recesses are located adjacent to a relatively central region of the top surface. The second recesses are located adjacent to a relatively peripheral region of the top surface. The first recess has a shape different from the second recess from a top-view perspective. The adhesive layer is disposed on the die paddle to fill into the first recesses. The III-nitride-based die is disposed on the adhesive layer. The encapsulant encapsulates the lead frame and the III-nitride-based die. The second recesses are filled with the encapsulant. The bonding wire is encapsulated by the encapsulant.