A semiconductor device includes: an insulating circuit substrate; a semiconductor element including a first main electrode bonded to a first conductor layer of the insulating circuit substrate via a first bonding material, a semiconductor substrate deposited on the first main electrode, and a second main electrode deposited on the semiconductor substrate; and a resistive element including a bottom surface electrode bonded to a second conductor layer of the insulating circuit substrate via a second bonding material, a resistive layer with one end electrically connected to the bottom surface electrode, and a top surface electrode electrically connected to another end of the resistive layer, wherein the first main electrode includes a first bonded layer bonded to the first bonding material, the bottom surface electrode includes a second bonded layer bonded to the second bonding material, and the first bonded layer and the second bonded layer have a common structure.

An insulated gate turn-off thyristor has a layered structure including a p+ layer (e.g., a substrate), an n-epi layer, a p-well, vertical insulated gate regions formed in the p-well, and an p-layer over the p-well and between the gate regions, so that vertical npn and pnp transistors are formed. The p-well has an intermediate highly doped portion. When the gate regions are sufficiently biased, an inversion layer surrounds the gate regions, causing the effective base of the npn transistor to be narrowed to increase its beta. When the product of the betas exceeds one, controlled latch-up of the thyristor is initiated. The p-well's highly doped intermediate region enables improvement in the npn transistor efficiency as well as enabling more independent control over the characteristics of the n-type layer (emitter), the emitter-base junction characteristics, and the overall dopant concentration and thickness of the p-type base.

A semiconductor device encompasses a cooler made of ceramics, having a first main face and a second main face, being parallel and opposite to the first main face, defined by two opposite side faces perpendicular to the first and second main faces, a plurality of conductive-pattern layers delineated on the first main face, a semiconductor chip mounted on the first main face via one of the plurality of conductive-pattern layers, and a seal member configured to seal the semiconductor chip.

In one embodiment, a power semiconductor module includes a main substrate, semiconductor chips mounted on the main substrate, and an auxiliary substrate also mounted on the main substrate. The power semiconductor module is capable of handling a current of 10 A or more. The auxiliary substrate is a printed circuit board having at least one carrier layer that is based on an organic material. The auxiliary substrate provides a common contact platform for at least some of the first semiconductor chips. The auxiliary substrate is attached to the main substrate by a joining layer located at a bottom side of the at least one auxiliary substrate facing the main substrate. The joining layer is a continuous organic adhesive layer of an adhesive foil or a double-faced adhesive tape.

The silicon carbide semiconductor chip includes a silicon carbide substrate, a first insulating film on the silicon carbide substrate, and a second insulating film on the first insulating film. The silicon carbide substrate has a first main surface in contact with the first insulating film, a second main surface, and an outer peripheral surface. The resin covers both of the outer peripheral surface and the second insulating film. The second insulating film has a Young's modulus lower than that of the resin. The second insulating film has a thermal expansion coefficient higher than that of the silicon carbide substrate and higher than that of the resin. The second insulating film includes a first outer peripheral end portion. In a cross section perpendicular to the first main surface, the first outer peripheral end portion is provided along the outer peripheral surface.

A semiconductor device includes: a plurality of semiconductor chips each including a first main electrode on a top surfaces and including a second main electrode and a control electrode on a bottom surface; a first common main electrode connected to the first main electrodes; a printed board including a control wiring part and a main wiring part provided on a bottom surface of an insulating layer, and a common control electrode and a second common main electrode provided on a top surface of the insulating layer and electrically connected to the control wiring part and the main wiring part; projection electrodes bonding the control electrodes to the control wiring part; projection electrodes bonding the second main electrodes to the main wiring part; and a sealing member sealing the semiconductor chips and exposing the first common main electrode, the common control electrode, and the second common main electrode.

A semiconductor device includes: a plurality of semiconductor chips each including a first main electrode on a top surfaces and including a second main electrode and a control electrode on a bottom surface; a first common main electrode connected to the first main electrodes; a printed board including a control wiring part and a main wiring part provided on a bottom surface of an insulating layer, and a common control electrode and a second common main electrode provided on a top surface of the insulating layer and electrically connected to the control wiring part and the main wiring part; projection electrodes bonding the control electrodes to the control wiring part; projection electrodes bonding the second main electrodes to the main wiring part; and a sealing member sealing the semiconductor chips and exposing the first common main electrode, the common control electrode, and the second common main electrode.

The silicon carbide semiconductor chip includes a silicon carbide substrate, a first insulating film on the silicon carbide substrate, and a second insulating film on the first insulating film. The silicon carbide substrate has a first main surface in contact with the first insulating film, a second main surface, and an outer peripheral surface. The resin covers both of the outer peripheral surface and the second insulating film. The second insulating film has a Young's modulus lower than that of the resin. The second insulating film has a thermal expansion coefficient higher than that of the silicon carbide substrate and higher than that of the resin. The second insulating film includes a first outer peripheral end portion. In a cross section perpendicular to the first main surface, the first outer peripheral end portion is provided along the outer peripheral surface.

DBC type structure, comprising an insulating support (22) coated with at least one conductive zone (20a) able to receive an electronic device, the conductive zone (20a) being in contact with the support (22), the insulating support incorporating means for thermal smoothing of the heat peak released by the component, these means comprising a cavity filled with a phase change material.

An electronics package includes an insulating substrate, a first electrical component coupled to a first surface of the insulating substrate, and a first conductor layer formed on the first surface of the insulating substrate. A second conductor layer is formed on a second surface of the insulating substrate, opposite the first surface, the second conductor layer extending through vias in the insulating substrate to contact at least one contact pad of the first electrical component and couple with the first conductor layer. The electronics package also includes a second electrical component having at least one contact pad coupled to the first conductor layer. The first conductor layer has a thickness greater than a thickness of the second conductor layer.