In an optical receiver circuit which suppresses an unnecessary increase in impedance and occurrences of resonance and radiation noise and which produces preferable high-frequency transmission characteristics, a PD submount mounted with a PD chip and a chip capacitor and a TIA carrier mounted with a TIA chip are electrically connected to each other by a bonding wire. The chip includes an anode electrode pad and a cathode electrode pad, anode electrode-side ground pads are formed at positions that sandwich the pad, and cathode electrode-side ground pads are formed at positions that sandwich the pad. A wire electrically connects the pad and a signal pad for input of the chip to each other, a wire electrically connects the pad and the capacitor to each other, and a wire electrically connects the pads and the pads to each other.

For example, a semiconductor device includes one or more first subcontacts electrically conducted to a substrate. At least one of the one or more first subcontacts is formed in an element arrangement region, and has a lower impedance than the substrate. Preferably, at least one of the one or more first subcontacts is adjacent to a circuit element formed in the element arrangement region. Preferably, on the substrate, which is of a first conductivity type, an epilayer of a second conductivity type is formed, and the one or more first subcontacts include a first line having a lower impedance than the substrate, and a semiconductor region of the first conductivity type penetrating through the epilayer to electrically conduct the first line and the substrate to each other.

A package for a current sense circuit may include a lead-frame having a shunt resistance configured to generate a shunt voltage, which can be used to measure a current through the lead-frame. The shunt resistance associated with the lead-frame may be highly variable with temperature, which can cause errors in the current measurement. Accordingly, a current sense circuit can include an amplifier with an input resistor having a composite temperature coefficient configured to match a lead-frame temperature coefficient so that an output of the amplifier is compensated to remove variations in the shunt resistance of the lead-frame due to temperature.

Electrical current flow in a ball grid array (BGA) package can be measured by an apparatus including an integrated circuit (IC) electrically connected to the BGA package. Solder balls connect the BGA package to a printed circuit board (PCB) and are arranged to provide a contiguous channel for a current sense wire. A subset of solder balls is electrically connected to supply current from the PCB through the BGA package to the IC. The current sense wire is attached to the upper surface of the PCB, within the contiguous channel, and surrounds the subset of solder balls. An amplifier is electrically connected to the current sense wire ends to amplify a voltage induced on the current sense wire by current flow into the BGA package. A sensing analog-to-digital converter (ADC) is electrically connected to convert a voltage at the output of the amplifier into digital output signals.

The present application discloses a multi-die FPGA implementing a built-in analog circuit using an active silicon connection layer, and relates to the field of FPGA technology. The multi-die FPGA allows multiple small-scale and small-area dies to cascade to achieve large-scale and large-area FPGA products, reducing processing difficulties and improving chip production yields. Meanwhile, due to the existence of the active silicon connection layer, some circuit structures that are difficult to implement within the die and/or occupy a large die area and/or have a low processing requirement can be laid out in the silicon connection layer, solving the existing problems of making these circuit structures directly within the die. Part of the circuit structures can be implemented within the silicon connection layer and the rest in the die, which helps optimize the performance of FPGA products, improve system stability, and reduce system area.

Electrical current flow in a ball grid array (BGA) package can be measured by an apparatus including an integrated circuit (IC) electrically connected to the BGA package. Solder balls connect the BGA package to a printed circuit board (PCB) and are arranged to provide a contiguous channel for a current sense wire. A subset of solder balls is electrically connected to supply current from the PCB through the BGA package to the IC. The current sense wire is attached to the upper surface of the PCB, within the contiguous channel, and surrounds the subset of solder balls. An amplifier is electrically connected to the current sense wire ends to amplify a voltage induced on the current sense wire by current flow into the BGA package. A sensing analog-to-digital converter (ADC) is electrically connected to convert a voltage at the output of the amplifier into digital output signals.

A semiconductor chip has a first transistor that amplifies a first signal and outputs a second signal, a second transistor that amplifies the second signal and outputs a third signal, and a semiconductor substrate having a main surface parallel to a plane defined by first and second directions and which has the first and second transistors formed thereon. The main surface has thereon a first bump connected to a collector or drain of the first transistor, a second bump connected to an emitter or source of the first transistor, a third bump connected to a collector or drain of the second transistor, and a fourth bump connected to an emitter or source of the second transistor. The first bump is circular, the second through fourth bumps are rectangular or oval, and the area of each of the second through fourth bumps is larger than that of the first bump.

A module includes: a board having a first surface; a first component and a second component mounted on the first surface; and a wire disposed to extend across both the first component and the second component. The wire has one end and the other end that are both connected to the first surface, and the wire is grounded. As seen in a direction perpendicular to the first surface, the first component is located closer to the one end than the second component, a portion of the wire that is furthest from the first surface is located closer to the one end than to the other end, and the second component has an upper surface located lower than an upper surface of the first component.

There is provided an optical communication device capable of minimum suppressing inter-signal interference of inductors mounted to enable a transmission signal to be transmitted and received with a high frequency. The optical communication device comprises a sub-package as a subassembly in each of a plurality of signal channels. The sub-package includes a substrate on which an optical semiconductor and an IC are flip-chip connected. The optical semiconductor includes a pair of photodiodes receiving a differential optical signal and outputting a differential current signal. The IC includes a transimpedance amplifier converting the differential current signal from the optical semiconductor to a voltage signal. The optical semiconductor has a pair of inductors formed for each of the pair of photodiodes and a ground wiring formed so as to surround the formed pair of inductors.

A semiconductor memory device includes a first chip and a second chip overlaid on the first chip. The second chip includes a memory cell array provided between a second semiconductor substrate and the first chip in a first direction, and first and second wires between the memory cell array and the first chip. The memory cell array includes three or more stacked bodies regularly arranged in a second direction perpendicular to the first direction and semiconductor layers extending in the stacked bodies in the first direction. Each of the stacked bodies includes gate electrodes stacked in the first direction. The first and second wires are aligned in the second direction with a gap therebetween.