H01L2924/1425

Integrated half-bridge power converter

An electronic power conversion component includes an electrically conductive package base comprising a source terminal, a drain terminal, at least one I/O terminal and a die-attach pad wherein the source terminal is electrically isolated from the die-attach pad. A GaN-based semiconductor die is secured to the die attach pad and includes a power transistor having a source and a drain, wherein the source is electrically coupled to the source terminal and the drain is electrically coupled to the drain terminal. A plurality of wirebonds electrically couple the source to the source terminal and the drain to the drain terminal. An encapsulant is formed over the GaN-based semiconductor die, the plurality of wirebonds and at least a top surface of the package base.

MULTI-INTERPOSER STRUCTURES AND METHODS OF MAKING THE SAME
20220415867 · 2022-12-29 ·

Various disclosed embodiments include a substrate, a first interposer coupled to the substrate and to a first semiconductor device die, and a second interposer coupled to the substrate and to a second semiconductor device die. The first semiconductor device die may be a serializer/de-serializer die and the first semiconductor device die coupled to the first interposer may be located proximate to a sidewall of the substrate. In certain embodiments, the second semiconductor device die may be a system-on-chip die. In further embodiments, the second interposer may also be coupled to high bandwidth memory die. Placing a serializer/de-serializer die proximate to a sidewall of a substrate allows a length of electrical pathways to be reduced, thus reducing impedance and RC delay. The use of smaller, separate, interposers also reduces complexity of fabrication of interposers and similarly lowers impedance associated with redistribution interconnect structures associated with the interposers.

INTEGRATED SEMICONDUCTOR DEVICE ISOLATION PACKAGE
20230094556 · 2023-03-30 ·

In a described example, an apparatus includes a transformer including: an isolation dielectric layer with a first surface and a second surface opposite the first surface; a first inductor formed over the first surface, the first inductor comprising a first layer of ferrite material, and a first coil at least partially covered by the first layer of ferrite material; and a second inductor formed over the second surface, the second inductor comprising a second layer of ferrite material and a second coil at least partially covered by the second layer of ferrite material.

DESIGN TECHNIQUE OF WIRING TO BE PROVIDED ON WIRING CIRCUIT BOARD TO BE MOUNTED IN ELECTRONIC APPARATUS
20230082556 · 2023-03-16 ·

An electronic apparatus comprises a semiconductor device and a mounting substrate. The semiconductor device includes a semiconductor chip and a wiring circuit board. The chip includes a circuit blocks and first electrode pads. The wiring circuit board includes a first surface and a second surface. The first surface includes second electrode pads wirings. The second surface includes ball electrodes. A first wiring supplies a ground potential to a first circuit block. A second wiring supplies a ground potential to a second circuit block. The second surface includes a first extension pad and a second extension pad. The first extension pad and the second extension pad are disposed at positions at which they are connected to each other on the second surface side through a single ball electrode.

Heterogenous Integration Scheme for III-V/Si and Si CMOS Integrated Circuits
20230154912 · 2023-05-18 ·

A method includes bonding a III-V die directly to a Complementary Metal-Oxide-Semiconductor (CMOS) die to form a die stack. The III-V die includes a (111) semiconductor substrate, and a first circuit including a III-V based n-type transistor formed at a surface of the (111) semiconductor substrate. The CMOS die includes a (100) semiconductor substrate, and a second circuit including an n-type transistor and a p-type transistor on the (100) semiconductor substrate. The first circuit is electrically connected to the second circuit.

Semiconductor device having multiple contact clips

A semiconductor device includes a device carrier, a first semiconductor chip mounted on the device carrier and a second semiconductor chip mounted on the device carrier. Further, the semiconductor device includes a first contact clip bonded to a first electrode of the first semiconductor chip, a second contact clip bonded to a first electrode of the second semiconductor chip and an insulating connector configured to hold the first contact clip and the second contact clip together.

Apparatus and method for harvesting energy in an electronic device
09799816 · 2017-10-24 · ·

An apparatus, a method, and a computer program product are provided. The apparatus may be an electronic component. The electronic component includes at least one energy harvester coupled between at least one pair of hot and cold regions of the electronic component and configured to convert thermal energy to electrical energy in order to provide power to at least the electronic component, the at least one energy harvester including a radiative thermal channel or a conductive thermal channel. A first end of the conductive thermal channel is coupled to a first semiconductor material and a second end of the conductive thermal channel is coupled to a second semiconductor material, the first semiconductor material being coupled to the hot region and isolated from the cold region and the second semiconductor material being coupled to the cold region and isolated from the hot region.

Semiconductor Package Including Flip Chip Mounted IC and Vertically Integrated Inductor
20170338171 · 2017-11-23 ·

In one implementation, a semiconductor package includes an integrated circuit (IC) flip chip mounted on a first patterned conductive carrier, a second patterned conductive carrier situated over the IC, and a magnetic material situated over the second patterned conductive carrier. The semiconductor package also includes a third patterned conductive carrier situated over the magnetic material. The second patterned conductive carrier and the third patterned conductive carrier are electrically coupled so as to form windings of an integrated inductor in the semiconductor package.

Wind turbine assembly

A wind turbine assembly including a rotor system, a generator, a first converter, a second converter, and a controller system. The first converter includes a first bridge circuit having a plurality of switch members each having a controllable switch. The second converter includes a second bridge circuit having a plurality of switch members each having a controllable switch. The controller system is adapted to provide a drying operation for second converter including short circuiting the second converter with the controllable switches of the second bridge in circuit, and supplying power from the generator through the first converter to the short circuited second converter for drying the second converter.

POWER CONVERSION APPARATUS AND METHOD FOR MANUFACTURING THE SAME
20170288564 · 2017-10-05 ·

A second lead frame is set onto a conductive layer and a busbar. The second lead frame has holes previously formed at opposite ends thereof, and pieces of solder material or solder pieces are inserted into the holes. Then, the solder pieces are vibrated by an ultrasonically vibrating tool, whereby the solder pieces are melted without having a high temperature. The second lead frame is thus bonded to the conductive layer and the busbar. A semiconductor element and the busbar are connected by a first lead frame and the second lead frame. The connection structure thereof is such that the second lead frame to be bonded by ultrasonic bonding or other bonding methods is not directly in contact with the semiconductor element, which eliminates the risk of damage to the semiconductor element.