An array substrate includes a glass substrate GS, an alignment mark 29, and first traces 19. The glass substrate GS has a corner portion 30 having an outline defined by a first edge portion 11b1 and a second edge portion 11b2 crossing the first edge portion 11b1. The alignment mark 29 is disposed at the corner portion 30 and used as the positioning index in mounting a driver 21 and a flexible printed circuit board 13. The alignment mark 29 at least includes first and second side portions 29a, 29b parallel to the first and second edge portions 11b1, 11b2, respectively. One end of the second side portion 29b is continuous to one end of the first side portion 29a. The alignment mark 29 has an outline that is on a same plane with a reference line BL connecting other ends of the first side portion 29a and the second side portion 29b linearly. The first traces 19 include inclined portions 31 that are inclined with respect to the first and second side portions 29a, 29b along the reference line BL.

A display device invention includes a substrate on which a plurality of light emitting elements are disposed. A plurality of lines are disposed on an upper surface of the substrate. A plurality of upper pads are disposed on the upper surface of the substrate and electrically connected to the plurality of lines. A plurality of link lines are disposed on a lower surface of the substrate. A plurality of lower pads are disposed on the lower surface of the substrate and electrically connected to the plurality of link lines. A plurality of side lines electrically connect the plurality of upper pads and the plurality of lower pads. The plurality of side lines include a plurality of first side lines and a plurality of second side lines, and the plurality of first side lines and the plurality of second side lines are disposed on different layers.

An integrated circuit (IC) chip includes a via contact plug extending inside a through hole passing through a substrate and a device layer, a via contact liner surrounding the via contact plug, a connection pad liner extending along a bottom surface of the substrate, a dummy bump structure integrally connected to the via contact plug, and a bump structure connected to the connection pad liner. A method of manufacturing an IC chip includes forming an under bump metallurgy (UBM) layer inside and outside the through hole and forming a first connection metal layer, a second connection metal layer, and a third connection metal layer. The first connection metal layer covers the UBM layer inside the through hole, the second connection metal layer is integrally connected to the first connection metal layer, and the third connection metal layer covers the UBM layer on the connection pad liner.

A manufacturing method of a metal bump structure is provided. A driving base is provided. At least one pad and an insulating layer are formed on the driving base. The pad is formed on an arrangement surface of the driving base and has an upper surface. The insulating layer covers the arrangement surface of the driving base and the pad, and exposes a part of the upper surface of the pad. A patterned metal layer is formed on the upper surface of the pad exposed by the insulating layer, and extends to cover a part of the insulating layer. An electro-less plating process is performed to form at least one metal bump on the patterned metal layer. A first extension direction of the metal bump is perpendicular to a second extension direction of the driving base.

An electronic device includes a plurality of light emitting units, a plurality of sensing units, and a sensor driving unit. The plurality of light emitting units are disposed on a first substrate. The plurality of sensing units correspond to the plurality of light emitting units, and the plurality of light emitting units and the plurality of sensing units are disposed in a same region. The sensor driving unit is coupled to at least a portion of the plurality of sensing units, and the plurality of light emitting units and the sensor driving unit are partially overlapped with each other.

A display device includes a display panel including a display area and a non-display area defined therein and including a plurality of signal pads overlapping the non-display area, an electronic component including a base layer with an upper surface and a lower surface, a plurality of driving pads disposed on the lower surface of the base layer, and a plurality of driving bumps respectively disposed on the plurality of driving pads, the plurality of driving bumps being respectively connected to the signal pads, and a filler disposed between the display panel and the electronic component. A first hole is defined in the upper surface of the base layer, and the first hole does not overlap the plurality of driving bumps in a plan view.

An IC chip includes I/O bumps on a back side, a first die, a second die, a first circuit, and a second circuit. The first die has driver circuits for LED devices, the LED devices being located on a front-facing surface of the first die. The first circuit extends from the front side toward the back side and across a thickness of the first die. The first circuit provides electrical connections between the LED devices and at least some of the I/O bumps. The first die and the second die can be stacked vertically or arranged laterally adjacent. The second circuit extends between the first die and the second die to electrically connect the first die and the second die. A circuit board can be electrically connected to the IC chip through the I/O bumps to, among other things, provide power to the various components of the IC chip.

An optoelectronic device includes a first semiconductor die, having first front and rear surfaces and including at least one avalanche photodetector configured to output electrical pulses in response to photons incident on the first front surface. A second semiconductor die has a second front surface, which is bonded to the first rear surface, and a second rear surface, and includes a photodetector receiver analog circuit coupled to the at least one avalanche photodetector and an emitter driver circuit configured to drive a pulsed optical emitter. A third semiconductor die has a third front surface, which is bonded to the second rear surface, and a third rear surface, and includes logic circuits coupled to control the photodetector receiver analog circuit and the emitter driver circuit and to receive and process the electrical pulses output by the at least one avalanche photodetector.

A chip structure including a chip body and a plurality of conductive bumps. The chip body includes an active surface and a plurality of bump pads disposed on the active surface. The conductive bumps are disposed on the active surface of the chip body and connected to the bump pads respectively, and at least one of the conductive bumps has a trapezoid shape having one pair of parallel sides and one pair of non-parallel sides.

A chip-on-film package includes a base film having a top surface and a bottom surface, and a circuit region; a source driver chip and a gate driver chip mounted on the circuit region; a first conductive line on the top surface of the base film, a second conductive line on the bottom surface of the base film, and a conductive via that connects the first and second conductive lines to each other; a first row of bonding pads on the circuit region and connected to the source driver chip; a second row of bonding pads on the circuit region and connected to the source driver chip and the gate driver chip; and a test pad outside the circuit region and connected to the first and second conductive lines and the conductive via.