A method of preparing a semiconductor substrate with metal bumps on both sides of the substrate. The method includes depositing a first-side UBM layer on a first surface of the semiconductor substrate. The method includes forming a plurality of first-side metal bumps on the first surface of the semiconductor substrate after the first-side UBM layer is deposited. The method includes forming a second-side UBM layer on a second side of the semiconductor substrate. The method includes forming a plurality of second-side metal bumps on the second surface of the semiconductor substrate after the second-side UBM layer is deposited. The method includes removing exposed first-side UBM layer and exposed second-side UBM layer after the plurality of first-side metal bumps and the plurality of second-side metal bumps are formed. The method includes reflowing the plurality of first-side metal bumps and the plurality of second side metal bumps.

An object is to provide a technique capable of enhancing electrical characteristics and reliability of a semiconductor device. The semiconductor device includes a plurality of semiconductor chips, a plurality of electrodes each being electrically connected to each of the plurality of semiconductor chips, a sealing member, and a joint part. The sealing member covers the plurality of semiconductor chips, and parts being connected to the plurality of semiconductor chips, of the plurality of electrodes. The joint part is disposed outside the sealing member to electrically connect parts which are not covered by the sealing member, of the plurality of electrodes.

A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die. Alternatively, the second semiconductor die is mounted to an interposer disposed over the interconnect structure.

A chip card manufacturing method. A module includes a substrate supporting contacts on one surface and conductive paths and a chip on another; and an antenna on a holder, the antenna including a contact pad for respectively connecting to each of the ends thereof. A solder drop is placed on each of the contact pads of the antenna. The holder of the antenna is inserted between plastic layers. A cavity is provided, in which the module can be accommodated and the solder drops remain accessible. The height of the solder drops before heating is suitable for projecting into the cavity. A module is placed in each cavity. The areas of the module that are located on the solder drops are heated to melt the solder and to solder the contact pads of the antenna to conductive paths of the module.

A package structure, an electronic device and a method for manufacturing the package structure are presented. The package structure comprises: a substrate (100), a sensing module (200) disposed on an upper surface of the substrate (100) and electrically connected to the substrate (100), and a package colloid (300) disposed on the upper surface of the substrate (100) and coating at least one portion of the sensing module (200), wherein the sensing module (200) comprises a capacitive sensor (210) and an optical sensor (220), and the package colloid (300) comprises at least one portion of a photic zone (310) disposed corresponding to the optical sensor (220). Thus, the capacitive sensor and the optical sensor can be packaged in one package structure, so as to improve the degree of integration of the package structure and save the package space.

An optoelectronic module is provided that has a carrier element, an optoelectronic element on the carrier element, a cover, and a cavity. The cover has a frame surrounding the optoelectronic element and connected to the carrier element. A glass element is on the frame lying substantially opposite the carrier element for the input and/or output of electromagnetic radiation. The cavity is inside a volume that is delimited by an inner surface of the cover and a surface of the carrier element. The optoelectronic element is arranged in the cavity and enclosed by the cover hermetically and/or in an autoclavable fashion. A filler material is in the cavity to compensate for an expansion of a volume occupied by the filler material and has a first deformable compensation volume, which is arranged adjacent to a subregion of the cover and/or of the carrier element.

A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die. Alternatively, the second semiconductor die is mounted to an interposer disposed over the interconnect structure.

The present invention relates to a chip-on film type semiconductor package including an integrated circuit chip, a printed circuit board layer, and a graphite layer, in which the integrated circuit chip is connected to one surface of the printed circuit board layer directly or by means of a mounting element and the graphite layer is laminated on an opposite surface of the printed circuit board layer and a display device including the same.

A self-powered electronic system comprises a first chip of single-crystalline semiconductor embedded in a second chip of single-crystalline semiconductor shaped as a container bordered by ridges. The assembled chips are nested and form an electronic device assembled, in turn, in a slab of weakly p-doped low-grade silicon shaped as a container bordered by ridges. The flat side of the slab includes a heavily n-doped region forming a pn-junction with the p-type bulk. A metal-filled deep silicon via through the p-type ridge connects the n-region with the terminal on the ridge surface as cathode of the photovoltaic cell with the p-region as anode. The voltage across the pn-junction serves as power source of the device.

A semiconductor device has a first semiconductor die and a modular interconnect structure adjacent to the first semiconductor die. An encapsulant is deposited over the first semiconductor die and modular interconnect structure as a reconstituted panel. An interconnect structure is formed over the first semiconductor die and modular interconnect structure. An active area of the first semiconductor die remains devoid of the interconnect structure. A second semiconductor die is mounted over the first semiconductor die with an active surface of the second semiconductor die oriented toward an active surface of the first semiconductor die. The reconstituted panel is singulated before or after mounting the second semiconductor die. The first or second semiconductor die includes a microelectromechanical system (MEMS). The second semiconductor die includes an encapsulant and an interconnect structure formed over the second semiconductor die. Alternatively, the second semiconductor die is mounted to an interposer disposed over the interconnect structure.