Disclosed is a semiconductor device including a semiconductor die, a base member, a side wall, first and second conductive films, and first and second conductive leads. The base member has a conductive main surface including a region that mounts the semiconductor die. The side wall surrounds the region and is made of a dielectric. The side wall includes first and second portions. The first and second conductive films are provided on the first and second portions, respectively and are electrically connected to the semiconductor die. The first and second conductive leads are conductively bonded to the first and second conductive films, respectively. At least one of the first and second portions includes a recess on its back surface facing the base member, and the recess defines a gap between the at least one of the first and second portions below the corresponding conductive film and the base member.

A semiconductor device according to one embodiment includes: a semiconductor chip having a transistor and a drain pad provided on a board; a capacitor having an upper electrode and a lower electrode interposing a dielectric; a pad; and an empty pad provided on the board of the semiconductor chip. The semiconductor device further includes: a first wire connecting the pad and the drain pad of the semiconductor chip to each other; a second wire connecting the empty pad and the upper electrode of the capacitor to each other; and a third wire connecting the pad and the empty pad to each other.

Disclosed is a package for a semiconductor device including a semiconductor die. The package includes a base member, a side wall, first and second conductive films, and first and second conductive leads. The base member has a conductive main surface including a region that mounts the semiconductor die. The side wall surrounds the region and is made of a dielectric. The side wall includes first and second portions. The first and second conductive films are provided on the first and second portions, respectively and are electrically connected to the semiconductor die. The first and second conductive leads are conductively bonded to the first and second conductive films, respectively. At least one of the first and second portions includes a recess in its back surface facing the base member, and the recess defines a gap between the at least one of the first and second portions below the corresponding conductive film and the base member.

An RF flip chip is provided in which a local bump region adjacent a die corner includes a balun having a centrally-located bump.

An RF flip chip is provided in which a local bump region adjacent a die corner includes a balun having a centrally-located bump.

Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a radio frequency (RF) die having a lateral surface area and a plurality of contacts on a face, where the RF die is embedded in the package substrate with the plurality of contacts facing towards the second surface of the package substrate, and an RF front end between the RF die and the first surface of the package substrate, where the RF front end is positioned under the RF die and does not extend beyond the lateral surface area of the RF die.

An RF flip chip is provided in which a local bump region adjacent a die corner includes a balun having a centrally-located bump.

In a transistor formed on a semiconductor die mounted on a substrate, where the transistor output is connected to a circuit on the substrate, a bond pad electrically connected to a transistor drain finger manifold extends less than the full length of the manifold. By controlling the length of the bond pad, the parasitic capacitance it contributes may be controlled. In applications such as a Doherty amplifier, this parasitic capacitance forms part of the quarter-wave transmission line of an impedance inverter, and hence directly impacts amplifier performance. In particular, by reducing the parasitic capacitance contribution from transistor output bond pads, the bandwidth of a Doherty amplifier circuit may be improved. At GHz frequencies and with state of the art transistor device feature sizes, concerns about phase mismatch between drain finger outputs are largely moot.

Disclosed is a semiconductor device including a semiconductor die, a base member, a side wall, first and second conductive films, and first and second conductive leads. The base member has a conductive main surface including a region that mounts the semiconductor die. The side wall surrounds the region and is made of a dielectric. The side wall includes first and second portions. The first and second conductive films are provided on the first and second portions, respectively and are electrically connected to the semiconductor die. The first and second conductive leads are conductively bonded to the first and second conductive films, respectively. At least one of the first and second portions includes a recess on its back surface facing the base member, and the recess defines a gap between the at least one of the first and second portions below the corresponding conductive film and the base member.

In a transistor formed on a semiconductor die mounted on a substrate, where the transistor output is connected to a circuit on the substrate, a bond pad electrically connected to a transistor drain finger manifold extends less than the full length of the manifold. By controlling the length of the bond pad, the parasitic capacitance it contributes may be controlled. In applications such as a Doherty amplifier, this parasitic capacitance forms part of the quarter-wave transmission line of an impedance inverter, and hence directly impacts amplifier performance. In particular, by reducing the parasitic capacitance contribution from transistor output bond pads, the bandwidth of a Doherty amplifier circuit may be improved. At GHz frequencies and with state of the art transistor device feature sizes, concerns about phase mismatch between drain finger outputs are largely moot.