A multi-pin wafer level chip scale package is achieved. One or more solder pillars and one or more solder blocks are formed on a silicon wafer wherein the one or more solder pillars and the one or more solder blocks all have a top surface in a same horizontal plane. A pillar metal layer underlies the one or more solder pillars and electrically contacts the one or more solder pillars with the silicon wafer through an opening in a polymer layer over a passivation layer. A block metal layer underlies the one or more solder blocks and electrically contacts the one or more solder pillars with the silicon wafer through a plurality of via openings through the polymer layer over the passivation layer wherein the block metal layer is thicker than the pillar metal layer.

A multi-pin wafer level chip scale package is achieved. One or more solder pillars and one or more solder blocks are formed on a silicon wafer wherein the one or more solder pillars and the one or more solder blocks all have a top surface in a same horizontal plane. A pillar metal layer underlies the one or more solder pillars and electrically contacts the one or more solder pillars with the silicon wafer through an opening in a polymer layer over a passivation layer. A block metal layer underlies the one or more solder blocks and electrically contacts the one or more solder pillars with the silicon wafer through a plurality of via openings through the polymer layer over the passivation layer wherein the block metal layer is thicker than the pillar metal layer.

A material for Cu pillars is formed as cylindrical preforms in advance and connecting these cylindrical preforms to electrodes on a semiconductor chip to form Cu pillars. Due to this, it becomes possible to make the height/diameter ratio of the Cu pillars 2.0 or more. Since electroplating is not used, the time required for production of the Cu pillars is short and the productivity can be improved. Further, the height of the Cu pillars can be raised to 200 μm or more, so these are also preferable for moldunderfill. The components can be freely adjusted, so it is possible to easily design the alloy components to obtain highly reliable Cu pillars.

A material for Cu pillars is formed as cylindrical preforms in advance and connecting these cylindrical preforms to electrodes on a semiconductor chip to form Cu pillars. Due to this, it becomes possible to make the height/diameter ratio of the Cu pillars 2.0 or more. Since electroplating is not used, the time required for production of the Cu pillars is short and the productivity can be improved. Further, the height of the Cu pillars can be raised to 200 μm or more, so these are also preferable for moldunderfill. The components can be freely adjusted, so it is possible to easily design the alloy components to obtain highly reliable Cu pillars.

A semiconductor device includes a semiconductor substrate, a conductive pad on the semiconductor substrate, and a conductor over the conductive pad. The semiconductor device further has a molding compound surrounding the semiconductor substrate, the conductive pad and the conductor. In the semiconductor device, the conductor has a stud shape.

A material for Cu pillars is formed as cylindrical preforms in advance and connecting these cylindrical preforms to electrodes on a semiconductor chip to form Cu pillars. Due to this, it becomes possible to make the height/diameter ratio of the Cu pillars 2.0 or more. Since electroplating is not used, the time required for production of the Cu pillars is short and the productivity can be improved. Further, the height of the Cu pillars can be raised to 200 μm or more, so these are also preferable for moldunderfill. The components can be freely adjusted, so it is possible to easily design the alloy components to obtain highly reliable Cu pillars.

A material for Cu pillars is formed as cylindrical preforms in advance and connecting these cylindrical preforms to electrodes on a semiconductor chip to form Cu pillars. Due to this, it becomes possible to make the height/diameter ratio of the Cu pillars 2.0 or more. Since electroplating is not used, the time required for production of the Cu pillars is short and the productivity can be improved. Further, the height of the Cu pillars can be raised to 200 μm or more, so these are also preferable for moldunderfill. The components can be freely adjusted, so it is possible to easily design the alloy components to obtain highly reliable Cu pillars.

A multi-pin wafer level chip scale package is achieved. One or more solder pillars and one or more solder blocks are formed on a silicon wafer wherein the one or more solder pillars and the one or more solder blocks all have a top surface in a same horizontal plane. A pillar metal layer underlies the one or more solder pillars and electrically contacts the one or more solder pillars with the silicon wafer through an opening in a polymer layer over a passivation layer. A block metal layer underlies the one or more solder blocks and electrically contacts the one or more solder pillars with the silicon wafer through a plurality of via openings through the polymer layer over the passivation layer wherein the block metal layer is thicker than the pillar metal layer.

A multi-pin wafer level chip scale package is achieved. One or more solder pillars and one or more solder blocks are formed on a silicon wafer wherein the one or more solder pillars and the one or more solder blocks all have a top surface in a same horizontal plane. A pillar metal layer underlies the one or more solder pillars and electrically contacts the one or more solder pillars with the silicon wafer through an opening in a polymer layer over a passivation layer. A block metal layer underlies the one or more solder blocks and electrically contacts the one or more solder pillars with the silicon wafer through a plurality of via openings through the polymer layer over the passivation layer wherein the block metal layer is thicker than the pillar metal layer.

Various embodiments provide for a chip package including a carrier; a layer over the carrier; a further carrier material over the layer, the further carrier material comprising a foil; one or more openings in the further carrier material, wherein the one or more openings expose at least one or more portions of the layer from the further carrier material; and a chip comprising one or more contact pads, wherein the chip is adhered to the carrier via the one or more exposed portions of the layer.