Various embodiments provide for a chip package including a carrier; a layer over the carrier; a further carrier material over the layer, the further carrier material comprising a foil; one or more openings in the further carrier material, wherein the one or more openings expose at least one or more portions of the layer from the further carrier material; and a chip comprising one or more contact pads, wherein the chip is adhered to the carrier via the one or more exposed portions of the layer.

A semiconductor package includes: a base substrate; an interposer disposed on the base substrate, wherein the interposer includes a plurality of recesses in a bottom surface thereof; a semiconductor chip disposed on the interposer; a plurality of interposer connection terminals between the interposer and the base substrate, wherein the plurality of interposer connection terminals electrically connect the interposer to the base substrate; and a first underfill layer disposed between the interposer and the base substrate, wherein the first underfill layer at least partially surrounds the plurality of interposer connection terminals, wherein the first underfill layer at least partially surrounds a side surface of each of the plurality of recesses and has a slope declining from the bottom surface of the interposer to a top surface of the base substrate.

Various embodiments provide for a chip package including a carrier; a layer over the carrier; a further carrier material over the layer, the further carrier material comprising a foil; one or more openings in the further carrier material, wherein the one or more openings expose at least one or more portions of the layer from the further carrier material; and a chip comprising one or more contact pads, wherein the chip is adhered to the carrier via the one or more exposed portions of the layer.

Various embodiments provide for a chip package consisting of a layer over a carrier, further carrier material over the layer, wherein one or more portions of the further carrier material is removed, and a chip with one or more contact pads, where the chip is adhered to the carrier via the layer. A wafer level package consisting of a plurality of chips adhered to the carrier via a plurality of portions of the layer released from the further carrier material is also provided for.

A semiconductor device of the present invention includes a semiconductor element, a surface electrode formed on a surface of the semiconductor element, a metal film formed on the surface electrode so as to have a joining portion and a stress relieving portion formed so as to border on and surround the joining portion, solder joined to the joining portion while avoiding the stress relieving portion, and an external electrode joined to the joining portion through the solder.

In some examples, a wafer chip scale package (WCSP) comprises a semiconductor die having a device side in which circuitry is formed and a non-device side opposite the device side, a solder bump electrically coupled to the circuitry, and a mold compound in contact with the device side, the solder bump, and four lateral sides of the semiconductor die. The package also comprises a thermal pad in contact with the non-device side of the semiconductor die and the mold compound.

A semiconductor device of the present invention includes a semiconductor element, a surface electrode formed on a surface of the semiconductor element, a metal film formed on the surface electrode so as to have a joining portion and a stress relieving portion formed so as to border on and surround the joining portion, solder joined to the joining portion while avoiding the stress relieving portion, and an external electrode joined to the joining portion through the solder.

A semiconductor device of the present invention includes a semiconductor element, a surface electrode formed on a surface of the semiconductor element, a metal film formed on the surface electrode so as to have a joining portion and a stress relieving portion formed so as to border on and surround the joining portion, solder joined to the joining portion while avoiding the stress relieving portion, and an external electrode joined to the joining portion through the solder.

A method forming a bond wire connection includes providing a wire bonder including a bond wedge with a wire guide, and forming a wire bond loop by initially bonding a bond wire to a first bonding surface using the bond wedge, then moving the wire bonder in a loop pattern whereby the bond wire passes through the wire guide, and then bonding the bond wire to a second bonding surface using the bond wedge, wherein moving the wire bonder in the loop pattern comprises a retrograde movement whereby the wire bonder moves away from the second bonding surface, and wherein the wire guide is formed from a material with a higher material hardness than the bond wire.