A semiconductor memory device includes first memory dies stacked one upon another and electrically connected one to another by first bond wires, and covered with a first encapsulant. Second memory dies are disposed above the first memory dies, stacked one upon another and electrically connected one to another with second bond wires, and covered with a second encapsulant. A control die may be mounted on the top die in the second die stack. Vertical bond wires extend between the stacked die modules. A redistribution layer is formed over the top die stack and the control die to allow for electrical communication with the memory device. The memory device allows for stacking memory dies in a manner that allows for increased memory capacity without increasing the package form factor.

A semiconductor memory device includes first memory dies stacked one upon another and electrically connected one to another by first bond wires, and covered with a first encapsulant. Second memory dies are disposed above the first memory dies, stacked one upon another and electrically connected one to another with second bond wires, and covered with a second encapsulant. A control die may be mounted on the top die in the second die stack. Vertical bond wires extend between the stacked die modules. A redistribution layer is formed over the top die stack and the control die to allow for electrical communication with the memory device. The memory device allows for stacking memory dies in a manner that allows for increased memory capacity without increasing the package form factor.

A self-densifying interconnection is formed between a high-temperature semiconductor device selected from a GaN or SiC-based device and a substrate. The interconnection includes a matrix of micron-sized silver particles in an amount from approximately 10 to 60 weight percent; the micron-sized silver particles having a particle size ranging from approximately 0.1 microns to 15 microns. Bonding particles are used to chemically bind the matrix of micron-sized silver particles. The bonding particles are core silver nanoparticles with in-situ formed surface silver nanoparticles chemically bound to the surface of the core silver nanoparticles and, at the same time, chemically bound to the matrix of micron-sized silver particles. The bonding particles have a core particle size ranging from approximately 10 to approximately 100 nanometers while the in-situ formed surface silver nanoparticles have a particle size of approximately 3-9 nanometers.

There is provided a copper bonding wire having an improved storage life in the atmosphere. There is specifically provided a copper bonding wire for semiconductor devices characterized in that a density of crystal grain boundary on a surface of the wire is 0.6 (μm/μm.sup.2) or more and 1.6 (μm/μm.sup.2) or less.

There is provided a copper bonding wire having an improved storage life in the atmosphere. There is specifically provided a copper bonding wire for semiconductor devices characterized in that a density of crystal grain boundary on a surface of the wire is 0.6 (μm/μm.sup.2) or more and 1.6 (μm/μm.sup.2) or less.

A semiconductor device includes a semiconductor chip having a device forming surface on which a device structure is formed, a first conductive layer formed on the device forming surface of the semiconductor chip, a second conductive layer formed on the first conductive layer, a first wire that is connected to the second conductive layer and that is made of a material composed mainly of copper, and a third conductive layer that is formed between the first conductive layer and the second conductive layer and that includes a material harder than copper.

A semiconductor device includes a semiconductor chip having a device forming surface on which a device structure is formed, a first conductive layer formed on the device forming surface of the semiconductor chip, a second conductive layer formed on the first conductive layer, a first wire that is connected to the second conductive layer and that is made of a material composed mainly of copper, and a third conductive layer that is formed between the first conductive layer and the second conductive layer and that includes a material harder than copper.

The present application provides a chip package structure and an electronic device, which could reduce a chip package thickness and implement ultra-thinning of chip package. The chip package structure includes a chip, a substrate, a lead and a lead protection adhesive; the lead is configured to electrically connect the chip and the substrate; the lead protection adhesive is configured to support the lead, where a highest point of the lead protection adhesive is not higher than a highest point of an upper edge of the lead.

The present application provides a chip package structure and an electronic device, which could reduce a chip package thickness and implement ultra-thinning of chip package. The chip package structure includes a chip, a substrate, a lead and a lead protection adhesive; the lead is configured to electrically connect the chip and the substrate; the lead protection adhesive is configured to support the lead, where a highest point of the lead protection adhesive is not higher than a highest point of an upper edge of the lead.

A method for manufacturing a light emitting device includes: preparing a first substrate having an upper surface comprising an element placement region; placing a light emitting element in the element placement region; disposing an uncured, sheet-like light-transmissive member on the light emitting element and bringing an outer edge of a lower surface of the light-transmissive member into contact with an outer upper surface of the element placement region of the first substrate by pressing the light-transmissive member; and disposing a first protrusion portion along an outer edge of an upper surface of the light-transmissive member so that the first protrusion portion extends over the upper surface of the first substrate and the upper surface of the light-transmissive member.