A semiconductor package includes a package board, at least one semiconductor chip disposed on the package board, a molding member disposed on the package board and at least partially surrounding the at least one semiconductor chip, and a heat dissipation member disposed on the at least one semiconductor chip and the molding member. The molding member has first region in which a plurality of uneven structures are disposed, and a second region spaced apart from an external region by the plurality of uneven structures. The plurality of uneven structures protrude to a predetermined height away from the semiconductor chip, the molding member, and the heat dissipation member, and may be formed as a part of the head dissipation member, or formed separately.

A first side of a sensor wafer is bonded to a first side of a first logic wafer. The sensor wafer contains pixels configured to detect radiation that enters the sensor wafer through a second side of the sensor wafer opposite the first side. The first logic wafer contains circuitry configured to operate the pixels. The sensor wafer or the first logic wafer contains a protection diode. The first logic wafer is thinned from a second side of the first logic wafer opposite the first side. A through-substrate-via (TSV) is formed in the first logic wafer. The protection diode protects the sensor wafer or the first logic wafer from being damaged during the forming of the TSV. The second side of the first logic wafer is bonded to a second logic wafer. The sensor wafer is thinned from the second side of the sensor wafer.

A semiconductor die package includes a high dielectric constant (high-k) dielectric layer over a device region of a first semiconductor die that is bonded with a second semiconductor die in a wafer on wafer (WoW) configuration. A through silicon via (TSV) structure may be formed through the device region. The high-k dielectric layer has an intrinsic negative charge polarity that provides a coupling voltage to modify the electric potential in the device region. In particular, the electron carriers in high-k dielectric layer attracts hole charge carriers in device region, which suppresses trap-assist tunnels that result from surface defects formed during etching of the recess for the TSV structure. Accordingly, the high-k dielectric layer described herein reduces the likelihood of (and/or the magnitude of) current leakage in semiconductor devices that are included in the device region of the first semiconductor die.

A connective structure for bonding semiconductor devices and methods for forming the same are provided. The bonding structure includes an alpad structure, i.e., a thick aluminum-containing connective pad, and a substructure beneath the aluminum-containing pad that includes at least a pre-metal layer and a barrier layer. The pre-metal layer is a dense material layer and includes a density greater than the barrier layer and is a low surface roughness film. The high density pre-metal layer prevents plasma damage from producing charges in underlying dielectric materials or destroying subjacent semiconductor devices.

A semiconductor package includes a package board, at least one semiconductor chip disposed on the package board, a molding member disposed on the package board and at least partially surrounding the at least one semiconductor chip, and a heat dissipation member disposed on the at least one semiconductor chip and the molding member. The molding member has first region in which a plurality of uneven structures are disposed, and a second region spaced apart from an external region by the plurality of uneven structures. The plurality of uneven structures protrude to a predetermined height away from the semiconductor chip, the molding member, and the heat dissipation member, and may be formed as a part of the head dissipation member, or formed separately.

A first side of a sensor wafer is bonded to a first side of a first logic wafer. The sensor wafer contains pixels configured to detect radiation that enters the sensor wafer through a second side of the sensor wafer opposite the first side. The first logic wafer contains circuitry configured to operate the pixels. The sensor wafer or the first logic wafer contains a protection diode. The first logic wafer is thinned from a second side of the first logic wafer opposite the first side. A through-substrate-via (TSV) is formed in the first logic wafer. The protection diode protects the sensor wafer or the first logic wafer from being damaged during the forming of the TSV. The second side of the first logic wafer is bonded to a second logic wafer. The sensor wafer is thinned from the second side of the sensor wafer.