A semiconductor package includes a package board, at least one semiconductor chip disposed on the package board, a molding member disposed on the package board and at least partially surrounding the at least one semiconductor chip, and a heat dissipation member disposed on the at least one semiconductor chip and the molding member. The molding member has first region in which a plurality of uneven structures are disposed, and a second region spaced apart from an external region by the plurality of uneven structures. The plurality of uneven structures protrude to a predetermined height away from the semiconductor chip, the molding member, and the heat dissipation member, and may be formed as a part of the head dissipation member, or formed separately.

In a method of manufacturing a semiconductor package, a first semiconductor device is arranged on a package substrate. An electrostatic discharge structure is formed on at least one ground substrate pad exposed from an upper surface of the package substrate. A plurality of second semiconductor devices is stacked on the package substrate and spaced apart from the first semiconductor device, the electrostatic discharge structure being interposed between the first semiconductor device and the plurality of second semiconductor devices. A molding member is formed on the package substrate to cover the first semiconductor device and the plurality of second semiconductor devices.

A semiconductor device including: a first silicon layer including a first single crystal silicon and a plurality of first transistors; a first metal layer disposed over the first silicon layer; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, a connection path from the fifth metal layer to the second metal layer, where the connection path includes a via disposed through the second level, where the via has a diameter of less than 450 nm, where the fifth metal layer includes a global power distribution grid, and where a typical thickness of the fifth metal layer is greater than a typical thickness of the second metal layer by at least 50%.

A semiconductor device includes a semiconductor part, first and second electrodes, and first and second protective films. The first electrode is provided on the semiconductor part. The first protective film is provided on the semiconductor part and covers an outer edge of the first electrode. The second electrode is provided on the first electrode. The second electrode includes an outer edge partially covering the first protective film. The second protective film is provided on the semiconductor part and covers the first protective film and the outer edge of the second electrode.

Implementations of a semiconductor package may include a die; a first pad and a second pad, the first pad and the second pad each including a first layer and a second layer where the second layer may be thicker than the first layer. At least a first conductor may be directly coupled to the second layer of the first pad; at least a second conductor may be directly coupled to the second layer of the second pad; and an organic material may cover at least the first side of the die. The at least first conductor and the at least second conductor extend through openings in the organic material where a spacing between the at least first conductor and the at least second conductor may be wider than a spacing between the second layer of the first pad and the second layer of the second pad.

A semiconductor memory device includes a first semiconductor layer including a memory cell array; a second semiconductor layer including a first substrate and a page buffer circuit which is configured on the first substrate; a third semiconductor layer disposed between the first semiconductor layer and the second semiconductor layer in a vertical direction, and including a second substrate and a second logic circuit which is configured on an element region of the second substrate; and a first contact plug passing through a coupling region of the second substrate which overlaps the page buffer circuit in the vertical direction.

Disclosed are systems, devices and methods for utilizing an interconnect conductor to inhibit or reduce the likelihood of de-lamination of a passivation layer of an integrated circuit die. In some implementations, a metal layer in ohmic contact with an intrinsic region of a semiconductor substrate can be partially covered by a passivation layer such as a dielectric layer. An interconnect conductor electrically connected to the metal layer can include an extension that covers an edge of the passivation layer to thereby inhibit the edge from lifting up. In some implementations, the metal layer in combination with a contact pad also in ohmic contact with the intrinsic region can yield a conduction path through the intrinsic region during an electrostatic discharge (ESD) event. In such a configuration, the interconnect conductor can route the ESD charge to a ground.

A manufacturing method of a package includes at least the following steps. Contact vias are embedded in a semiconductor carrier. The contact vias are electrically grounded. A first die and a first encapsulant are provided over the semiconductor carrier. The first encapsulant encapsulates the first die. First through insulating vias (TIV) are formed aside the first die. The first TIVs are electrically grounded through the contact vias. The first die, the first encapsulant, and the first TIVs are grinded. A second die is stacked over the first die.

An ESD protection device may include: a first vertically integrated ESD protection structure comprising a first semiconductor portion, a first contact region disposed on a first side of the first semiconductor portion and a first terminal exposed on a second side of the first semiconductor portion opposite the first side of the first semiconductor portion, a second vertically integrated ESD protection structure comprising a second semiconductor portion, a second contact region disposed on a first side of the second semiconductor portion and a second terminal exposed on a second side of the second semiconductor portion opposite the first side of the second semiconductor portion, an electrical connection layer, wherein the first vertically integrated ESD protection structure and the second vertically integrated ESD protection structure are disposed on the electrical connection layer laterally separated from each other and are electrically connected with each other anti-serially via the electrical connection layer.

The present invention discloses a package structure and a method for forming the same. The package structure includes a substrate, a chip, a first plastic package layer and a support block, wherein the substrate includes a first surface and a second surface; the chip is disposed on the first surface; the first plastic package layer is disposed on the first surface and packages the chip; the support block is disposed on the second surface; and in a thickness direction of the substrate, an overlapping region exists between the chip and the support block, and a thermal expansion coefficient of the chip is equal to a thermal expansion coefficient of the support block. The support block can counteract part of stress to avoid problems such as warping or twisting. Due to the overlapping region, a counteraction function of the support block on the stress exerted on the chip can be improved.