Reliability of a semiconductor device is improved. A slope is provided on a side face of an interconnection trench in sectional view in an interconnection width direction of a redistribution layer. The maximum opening width of the interconnection trench in the interconnection width direction is larger than the maximum interconnection width of the redistribution layer in the interconnection width direction, and the interconnection trench is provided so as to encapsulate the redistribution layer in plan view.

There is provided a novel Cu bonding wire that achieves a favorable FAB shape and reduces a galvanic corrosion in a high-temperature environment to achieve a favorable bond reliability of the 2nd bonding part. The bonding wire for semiconductor devices includes a core material of Cu or Cu alloy, and a coating layer having a total concentration of Pd and Ni of 90 atomic % or more formed on a surface of the core material. The bonding wire is characterized in that: in a concentration profile in a depth direction of the wire obtained by performing measurement using Auger electron spectroscopy (AES) so that the number of measurement points in the depth direction is 50 or more for the coating layer, a thickness of the coating layer is 10 nm or more and 130 nm or less, an average value X is 0.2 or more and 35.0 or less where X is defined as an average value of a ratio of a Pd concentration C.sub.Pd (atomic %) to an Ni concentration C.sub.Ni (atomic %), C.sub.Pd/C.sub.Ni, for all measurement points in the coating layer, and the total number of measurement points in the coating layer whose absolute deviation from the average value X is 0.3X or less is 50% or more relative to the total number of measurement points in the coating layer.

Provided is a semiconductor package with improved reliability. The semiconductor package includes: a plurality of connection terminals on a first surface of the semiconductor device; a protection member on the first surface of the semiconductor device and partially covers side surfaces of the plurality of connection terminals such that the protective member exposes lower surfaces of the plurality of connection terminals; and a mold member that covers a side surface of the semiconductor device and a portion of the protection member such that the mold member does not cover the lower surfaces of the plurality of connection terminals.

The present invention discloses a package structure and a forming method thereof. The package structure includes a substrate and a redistribution layer. The redistribution layer includes a plurality of metal bumps distributed at intervals, at least the periphery of the metal bumps is covered with seed layers, and the seed layers of adjacent metal bumps are disconnected from each other. The seed layers of this embodiment have stable metallic characteristics, which may achieve effective protection of side walls of the metal bumps against metal-to-metal migration due to oxidation and corrosion of the metal bumps, thereby avoiding electrical leakage and failure of a chip and greatly increasing the reliability of the package structure.

In some aspects, the techniques described herein relate to an electronic device including: a substrate; a metallization layer, the metallization layer having: a first surface disposed on the substrate; a second surface opposite the first surface; and a corrosion-prevention implant layer disposed in the metallization layer, the corrosion-prevention implant layer extending from the second surface to a depth from the second surface in the metallization layer, the depth being less than a thickness of the metallization layer; and an electrical connector coupled with the second surface.

There is provided a bonding wire for semiconductor devices that exhibits a favorable bondability even when being applied to wedge bonding at the room temperature, and also achieves an excellent bond reliability. The bonding wire includes a core material of Cu or Cu alloy (hereinafter referred to as a “Cu core material”), and a coating containing a noble metal formed on a surface of the Cu core material. A concentration of Cu at a surface of the wire is 30 to 80 at%.

A wafer-to-wafer bonding structure includes a first wafer including a first conductive pad in a first insulating layer and a first barrier layer surrounding a lower surface and side surfaces of the first conductive pad, a second wafer including a second conductive pad in a second insulating layer and a second barrier layer surrounding a lower surface and side surfaces of the second conductive pad, the second insulating layer being bonded to the first insulating layer, and at least a portion of an upper surface of the second conductive pad being partially or entirely bonded to at least a portion of an upper surface of the first conductive pad, and a third barrier layer between portions of the first and second wafers where the first and second conductive pads are not bonded to each other.

Provided is a device in which the metal content existing in a joining interface is controlled. A manufacturing method for the device comprises: a step in which the surfaces of a first substrate and a second substrate are activated using a FAB gun; a step in which a plurality of metals are discharged by using the FAB gun to sputter a discharged metal body comprising the plurality of metals, and the plurality of metals are affixed to the surfaces of the first substrate and the second substrate; a step in which the first substrate and the second substrate are joined at room temperature; and a step in which heating is performed at a temperature that is high in comparison to the agglomeration start temperature of the plurality of metals and of the elements that constitute the first substrate or the second substrate. With regards to the step in which the plurality of metals are affixed, the density of the plurality of metals existing on the joining interface of the first substrate and the second substrate is set to 1×10.sup.12/cm.sup.2 or less by adjusting the exposure area of the discharged metal body.

In various embodiments, a chip package is provided. The chip package may include a chip including a chip metal surface, a metal contact structure electrically contacting the chip metal surface, and packaging material including a contact layer being in physical contact with the chip metal surface and/or with the metal contact structure; wherein at least in the contact layer of the packaging material, a summed concentration of chemically reactive sulfur, chemically reactive selenium and chemically reactive tellurium is less than 10 atomic parts per million.

In various embodiments, a chip package is provided. The chip package may include a chip comprising a chip metal surface, a metal contact structure electrically contacting the chip metal surface, a packaging material at least partially encapsulating the chip and the metal contact structure, and a chemical compound physically contacting the packaging material and at least one of the chip metal surface and the metal contact structure, wherein the chemical compound may be configured to improve an adhesion between the metal contact structure and the packaging material and/or between the chip metal surface and the packaging material, as compared with an adhesion in an arrangement without the chemical compound, wherein the chemical compound is essentially free from functional groups comprising sulfur, selenium or tellurium.