Electronic device package technology is disclosed. In one example, an electronic device comprises a die (18) having a bond pad (22); and a decoupling capacitor (14) mounted on the die (18) and electrically coupled to the die (18). A method for making an electronic device comprises mounting a decoupling capacitor (14) on a die (18); and electrically coupling the decoupling capacitor (14) to the die (18).

An integrated circuit package includes a lead frame, a first die adhered to the lead frame on a first side of the first die, and a first clip having a clip foot adhered to the lead frame. The first clip has a first side and a second side. A first die attachment region is defined by a first group of four notches in the first side of the first clip. The first clip extends from the lead frame and contacts a second side of the first die at the first die attachment region via a first layer of solder paste. The integrated circuit package further has a second die adhered to the second side of the first clip on a first side of the second die, and a second clip having a clip foot adhered to the lead frame. The second clip has a first side and a second side. A second die attachment region is defined by a second group of four notches in the first side of the second clip. The second clip extends from the lead frame and contacts a second side of the second die at the second die attachment region via a second layer of solder paste.

A method is disclosed for manufacturing a semiconductor device including a mounting substrate, a semiconductor chip, a rear-surface metal layer, an AuSn solder layer, and a solder blocking metal layer, is disclosed. The semiconductor chip is mounted on the mounting substrate, and includes front and rear surfaces, and a heat generating element. The rear-surface metal layer includes gold (Au). The AuSn solder layer is located between the mounting substrate and the rear surface to fix the semiconductor chip to the mounting substrate. The solder blocking metal layer is located between the rear surface and the mounting substrate, and in a non-heating region excluding a heating region in which the heat generating element is formed. The solder blocking metal layer includes at least one of NiCr, Ni and Ti and extends to an edge of the semiconductor chip. A void is provided between the solder blocking metal layer and the AuSn solder layer.

A semiconductor device including a mounting substrate, a semiconductor chip, a rear-surface metal layer, an AuSn solder layer, and a solder blocking metal layer, is disclosed. The semiconductor chip is mounted on the mounting substrate, and includes front and rear surfaces, and a heat generating element. The rear-surface metal layer includes gold (Au). The AuSn solder layer is located between the mounting substrate and the rear surface to fix the semiconductor chip to the mounting substrate. The solder blocking metal layer is located between the rear surface and the mounting substrate, and in a non-heating region excluding a heating region in which the heat generating element is formed. The solder blocking metal layer includes at least one of NiCr, Ni and Ti and extends to an edge of the semiconductor chip. A void is provided between the solder blocking metal layer and the AuSn solder layer.

A semiconductor device comprising a mounting substrate, a semiconductor chip, a rear-surface metal layer, an AuSn solder layer, and a solder blocking metal layer, is disclosed. The semiconductor chip is mounted on the mounting substrate, and includes front and rear surfaces, and a heat generating element. The rear-surface metal layer includes gold (Au). The AuSn solder layer is located between the mounting substrate and the rear surface to fix the semiconductor chip to the mounting substrate. The solder blocking metal layer is located between the rear surface and the mounting substrate, and in a non-heating region excluding a heating region in which the heat generating element is formed. The solder blocking metal layer includes at least one of NiCr, Ni and Ti and extends to an edge of the semiconductor chip. A void is provided between the solder blocking metal layer and the AuSn solder layer.

A semiconductor package includes a first semiconductor chip including a first semiconductor device, a second semiconductor chip including a second semiconductor device, and a bonding structure between the first and second semiconductor chips, the bonding structure including a first bonding pad, a first bonding insulating layer, a second bonding pad in contact with the first bonding pad, and a second bonding insulating layer in contact with the first bonding insulating layer. The first bonding pad may include a first pad metal layer and a first conductive barrier layer surrounding the first pad metal layer, and the first conductive barrier layer may include a horizontal extension portion extending on an edge of an upper surface of the first pad metal layer.

Electronic device package technology is disclosed. In one example, an electronic device comprises a die (18) having a bond pad (22); and a decoupling capacitor (14) mounted on the die (18) and electrically coupled to the die (18). A method for making an electronic device comprises mounting a decoupling capacitor (14) on a die (18); and electrically coupling the decoupling capacitor (14) to the die (18).

Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures included herein may include a die on a first substrate, at least one first component adjacent the die on the first substrate, and molding material on the first substrate, wherein the at least one component and the die are embedded in the molding material. A second substrate may be physically coupled to the first substrate. A communication structure may be disposed on a top surface of the second substrate, wherein at least one second component may also be located on the top surface of the second substrate.

Methods of forming microelectronic package structures/modules, and structures formed thereby, are described. Structures included herein may include a die on a first substrate, at least one first component adjacent the die on the first substrate, and molding material on the first substrate, wherein the at least one component and the die are embedded in the molding material. A second substrate may be physically coupled to the first substrate. A communication structure may be disposed on a top surface of the second substrate, wherein at least one second component may also be located on the top surface of the second substrate.

Embodiments of a semiconductor device including a floating bond pad are disclosed. In one preferred embodiment, the semiconductor device is a power semiconductor device. In one embodiment, the semiconductor device includes a substrate that includes an active area and a control contact area, a first bond pad on the active area, a floating control bond pad on the control contact area and laterally extending over a portion of the first bond pad, and a dielectric between the portion of the first bond pad and the floating control bond pad. The floating control bond pad enables the active area to extend below the floating control bond pad, which in turn decreases a size of the power semiconductor device for a particular rated current or, conversely, increases a size of the active area and thus a rated current for a particular semiconductor die size.