Microstructures of micro and/or nano holes on one or more surfaces enhance photodetector optical sensitivity. Arrangements such as a CMOS Image Sensor (CIS) as an imaging LIDAR using a high speed photodetector array wafer of Si, Ge, a Ge alloy on SI and/or Si on Ge on Si, and a wafer of CMOS Logic Processor (CLP) ib Si fi signal amplification, processing and/or transmission can be stacked for electrical interaction. The wafers can be fabricated separately and then stacked or can be regions of the same monolithic chip. The image can be a time-of-flight image. Bayer arrays can be enhanced with microstructure holes. Pixels can be photodiodes, avalanche photodiodes, single photon avalanche photodiodes and phototransistors on the same array and can be Ge or Si pixels. The array can be of high speed photodetectors with data rates of 56 Gigabits per second, Gbps, or more per photodetector.

A method and apparatus for reducing as-deposited and metastable defects relative to amorphous silicon (a-Si) thin films, its alloys and devices fabricated therefrom that include heating an earth shield positioned around a cathode in a parallel plate plasma chemical vapor deposition chamber to control a temperature of a showerhead in the deposition chamber in the range of 350° C. to 600° C. An anode in the deposition chamber is cooled to maintain a temperature in the range of 50° C. to 450° C. at the substrate that is positioned at the anode. In the apparatus, a heater is embedded within the earth shield and a cooling system is embedded within the anode.

Photovoltaic devices with very high breakdown voltages are described herein. Typical commercial silicon photovoltaic devices have breakdown voltages below 50-100 volts (V). Even though such devices have bypass diodes to prevent photovoltaic cells from going into breakdown, the bypass diodes have high failure rates, leading to unreliable devices. A high-efficiency silicon photovoltaic cell is provided with very high breakdown voltages. By combining a device architecture with very low surface recombination and silicon wafers with high bulk resistivity (above 10 ohms centimeter (Ω-cm)), embodiments described herein achieve breakdown voltages close to 1000 V. These photovoltaic cells with high breakdown voltages improve the reliability of photovoltaic devices, while reducing their design complexity and cost.

A number of monolithic multi-throw diode switch structures are described. The monolithic multi-throw diode switches can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, two PIN diodes in a monolithic multi-throw diode switch have different intrinsic region thicknesses. The first PIN diode has a thinner intrinsic region, and the second PIN diode has a thicker intrinsic region. This configuration allows for both the thin intrinsic region PIN diode and the thick intrinsic region PIN diode to be individually optimized. As one example, for a switch functioning in a dedicated transmit/receive mode, the first transmit PIN diode can have a thicker intrinsic region than the second receive PIN diode to maximize power handling for the transmit arm and maximize receive sensitivity and insertion loss in the receive arm.

A number of monolithic multi-throw diode switch structures are described. The monolithic multi-throw diode switches can include a hybrid arrangement of diodes with different intrinsic regions, all formed over the same semiconductor substrate. In one example, two PIN diodes in a monolithic multi-throw diode switch have different intrinsic region thicknesses. The first PIN diode has a thinner intrinsic region, and the second PIN diode has a thicker intrinsic region. This configuration allows for both the thin intrinsic region PIN diode and the thick intrinsic region PIN diode to be individually optimized. As one example, for a switch functioning in a dedicated transmit/receive mode, the first transmit PIN diode can have a thicker intrinsic region than the second receive PIN diode to maximize power handling for the transmit arm and maximize receive sensitivity and insertion loss in the receive arm.

A system for wafer processing, includes: a frame comprising a frame opening; and a membrane configured to couple to the frame and to cover at least a part of the frame opening, the membrane comprising a membrane opening, wherein the membrane opening has a membrane opening area that is equal to or less than a frame opening area of the frame opening; wherein the membrane is configured for coupling with the wafer, wherein when the wafer is coupled with the membrane, the wafer covers the membrane opening, and wherein the membrane is configured to maintain the wafer at a certain position with respect to the frame; and wherein the membrane opening area is less than a total area of the wafer.

A system for wafer processing, includes: a frame comprising a frame opening; and a membrane configured to couple to the frame and to cover at least a part of the frame opening, the membrane comprising a membrane opening, wherein the membrane opening has a membrane opening area that is equal to or less than a frame opening area of the frame opening; wherein the membrane is configured for coupling with the wafer, wherein when the wafer is coupled with the membrane, the wafer covers the membrane opening, and wherein the membrane is configured to maintain the wafer at a certain position with respect to the frame; and wherein the membrane opening area is less than a total area of the wafer.

Separation of individual strips from a solar cell workpiece, is accomplished by excluding a junction (e.g., a homojunction such as a p-n junction, or a heterojunction such as a p-i-n junction) from regions at which separation is expected to occur. According to some embodiments, the junction is excluded by physical removal of material from inter-strip regions of the workpiece. According to other embodiments, exclusion of the junction is achieved by changing an effective doping level (e.g., counter-doping, deactivation) at inter-strip regions. For still other embodiments, the junction is never formed at inter-strip regions in the first place (e.g., using masking during original dopant introduction). By imposing distance between the junction and defects arising from separation processes (e.g., backside crack propagation), losses attributable to electron-hole recombination at such defects are reduced, and collection efficiency of shingled modules is enhanced.

Separation of individual strips from a solar cell workpiece, is accomplished by excluding a junction (e.g., a homojunction such as a p-n junction, or a heterojunction such as a p-i-n junction) from regions at which separation is expected to occur. According to some embodiments, the junction is excluded by physical removal of material from inter-strip regions of the workpiece. According to other embodiments, exclusion of the junction is achieved by changing an effective doping level (e.g., counter-doping, deactivation) at inter-strip regions. For still other embodiments, the junction is never formed at inter-strip regions in the first place (e.g., using masking during original dopant introduction). By imposing distance between the junction and defects arising from separation processes (e.g., backside crack propagation), losses attributable to electron-hole recombination at such defects are reduced, and collection efficiency of shingled modules is enhanced.

A system for wafer processing, includes: a frame comprising a frame opening; and a membrane configured to couple to the frame and to cover at least a part of the frame opening, the membrane comprising a membrane opening, wherein the membrane opening has a membrane opening area that is equal to or less than a frame opening area of the frame opening; wherein the membrane is configured for coupling with the wafer, wherein when the wafer is coupled with the membrane, the wafer covers the membrane opening, and wherein the membrane is configured to maintain the wafer at a certain position with respect to the frame; and wherein the membrane opening area is less than a total area of the wafer.