A semiconductor device comprises a substrate, one or more first III-semiconductor layers, and a plurality of superlattice structures between the substrate and the one or more first layers. The plurality of superlattice structures comprises an initial superlattice structure and one or more further superlattice structures between the initial superlattice structure and the one or more first layers. The plurality of superlattice structures is configured such that a strain-thickness product of semiconductor layer pairs in each superlattice structure of the one or more further superlattice structures is greater than or equal to a strain-thickness product of semiconductor layer pairs in superlattice structure(s) of the plurality of superlattice structures between that superlattice structure and the substrate. The plurality of superlattice structures is also configured such that a strain-thickness product of semiconductor layer pairs in at least one of the one or more further superlattice structures is greater than a strain-thickness product of semiconductor layer pairs in the initial superlattice structure.

A semiconductor device comprises a substrate, one or more first III-semiconductor layers, and a plurality of superlattice structures between the substrate and the one or more first layers. The plurality of superlattice structures comprises an initial superlattice structure and one or more further superlattice structures between the initial superlattice structure and the one or more first layers. The plurality of superlattice structures is configured such that a strain-thickness product of semiconductor layer pairs in each superlattice structure of the one or more further superlattice structures is greater than or equal to a strain-thickness product of semiconductor layer pairs in superlattice structure(s) of the plurality of superlattice structures between that superlattice structure and the substrate. The plurality of superlattice structures is also configured such that a strain-thickness product of semiconductor layer pairs in at least one of the one or more further superlattice structures is greater than a strain-thickness product of semiconductor layer pairs in the initial superlattice structure.

A p-n junction based III-nitride device in which the p-type layers adjacent to the n-type layers are activated by thermal annealing with a porous n-type tunnel junction layer or layers. The porosity of the n-type tunnel junction layer(s) allows for gas exchange to occur, allowing efficient p-type nitride semiconductor activation. This porosification and activation step can be inserted wherever desired into an existing fabrication process for an LED, laser diode, or any other nitride semiconductor device. In one example, the device comprises multiple LED structures grown successively, separated by tunnel junctions and the buried p-type layers are activated by thermal annealing with adjacent porous n-type layers. Using this method, efficient monolithic multi-color LEDs can be formed.

A p-n junction based III-nitride device in which the p-type layers adjacent to the n-type layers are activated by thermal annealing with a porous n-type tunnel junction layer or layers. The porosity of the n-type tunnel junction layer(s) allows for gas exchange to occur, allowing efficient p-type nitride semiconductor activation. This porosification and activation step can be inserted wherever desired into an existing fabrication process for an LED, laser diode, or any other nitride semiconductor device. In one example, the device comprises multiple LED structures grown successively, separated by tunnel junctions and the buried p-type layers are activated by thermal annealing with adjacent porous n-type layers. Using this method, efficient monolithic multi-color LEDs can be formed.

A semiconductor light emitting device includes a multi-quantum-well structure, a first capping layer, a second capping layer, and an electron barrier layer stacked in order. The multi-quantum-well structure includes a plurality of alternately-stacked potential barrier layers and potential well layers. The first capping layer is a semiconductor layer, and the second capping layer is a p-doped semiconductor layer. Each of the first and second capping layers has an aluminum mole fraction larger than that of each of the potential barrier layers, and the aluminum mole fraction of the first capping layer is larger than that of at least a portion of the electron barrier layer. A method for preparing the semiconductor light emitting device is also provided.

An epitaxial wafer of a light-emitting chip, a method for manufacturing an epitaxial wafer, and a light-emitting chip are provided. A light-emitting layer (5) of an active region of the epitaxial wafer of the light-emitting chip includes at least one superlattice (51), and each superlattice includes: a quantum well sub-layer (511) and a stress conversion sub-layer (512) which is formed on the quantum well sub-layer (511) and enables the quantum well sub-layer (511) to be converted from compressive strain to tensile strain, and the stress conversion sub-layer (512) and the quantum well sub-layer (511) form a two-dimensional electron gas.

An optoelectronic semiconductor device comprises a barrier layer, a first semiconductor layer on the barrier layer, the first semiconductor layer comprising a first dopant and a second dopant, and a second semiconductor layer beneath the barrier layer, the second semiconductor comprising the second dopant, wherein, in the first semiconductor layer, a concentration of the first dopant is larger than a concentration of the second dopant, and the concentration of the second dopant in the second semiconductor layer is larger than that in the first semiconductor layer.

An optoelectronic semiconductor device comprises a barrier layer, a first semiconductor layer on the barrier layer, the first semiconductor layer comprising a first dopant and a second dopant, and a second semiconductor layer beneath the barrier layer, the second semiconductor comprising the second dopant, wherein, in the first semiconductor layer, a concentration of the first dopant is larger than a concentration of the second dopant, and the concentration of the second dopant in the second semiconductor layer is larger than that in the first semiconductor layer.

A nitride-based semiconductor light-emitting element includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer of a second conductivity type different from the first conductivity type; a carrier blocking layer of the second conductivity type, provided on a surface of the second semiconductor layer closer to the first semiconductor layer; and a light-emitting layer region having a light-emitting layer, provided between the first semiconductor layer and the carrier blocking layer. A predetermined specific region is provided in the carrier blocking layer and extending from an interface between the carrier blocking layer and the light-emitting layer region and wherein a maximum value of a concentration of an impurity of the second conductivity type in the predetermined specific region is higher than 5×10.sup.19 cm.sup.−3.

A light-emitting diode includes a material structure of barrier in the light-emitting well region to improve restriction capacity of electron holes, improving light-emitting efficiency of the LED chip under high temperature. The LED structure includes a Type I semiconductor layer, a Type II semiconductor layer and an active layer between the both, wherein, the active layer is a multi-quantum well structure alternatively composed of well layers and barrier layers, in which, the first barrier layer is a first AlGaN gradient layer in which aluminum components gradually increase in the direction from the Type I semiconductor layer to the quantum well, and the barrier layer at the middle of well layers is an AlGaN/GaN/AlGaN multi-layer barrier layer, and the last barrier layer is a second AlGaN gradient layer in which aluminum components gradually decrease in the direction from the quantum well to the Type II semiconductor layer.