A semiconductor device comprises a substrate, one or more first III-semiconductor layers, and a plurality of superlattice structures between the substrate and the one or more first layers. The plurality of superlattice structures comprises an initial superlattice structure and one or more further superlattice structures between the initial superlattice structure and the one or more first layers. The plurality of superlattice structures is configured such that a strain-thickness product of semiconductor layer pairs in each superlattice structure of the one or more further superlattice structures is greater than or equal to a strain-thickness product of semiconductor layer pairs in superlattice structure(s) of the plurality of superlattice structures between that superlattice structure and the substrate. The plurality of superlattice structures is also configured such that a strain-thickness product of semiconductor layer pairs in at least one of the one or more further superlattice structures is greater than a strain-thickness product of semiconductor layer pairs in the initial superlattice structure.

A semiconductor device comprises a substrate, one or more first III-semiconductor layers, and a plurality of superlattice structures between the substrate and the one or more first layers. The plurality of superlattice structures comprises an initial superlattice structure and one or more further superlattice structures between the initial superlattice structure and the one or more first layers. The plurality of superlattice structures is configured such that a strain-thickness product of semiconductor layer pairs in each superlattice structure of the one or more further superlattice structures is greater than or equal to a strain-thickness product of semiconductor layer pairs in superlattice structure(s) of the plurality of superlattice structures between that superlattice structure and the substrate. The plurality of superlattice structures is also configured such that a strain-thickness product of semiconductor layer pairs in at least one of the one or more further superlattice structures is greater than a strain-thickness product of semiconductor layer pairs in the initial superlattice structure.

Disclosed is an epitaxial substrate with a 2D material interposer on a surface of a polycrystalline substrate. The ultra-thin 2D material interposer is grown by van der Waals epitaxy. The lattice constant of a surface layer of the ultra-thin 2D material interposer and the coefficient of thermal expansion of the substrate base are highly fit with those of AlGaN or GaN. The ultra-thin 2D material interposer is of a single-layer structure or a composite-layer structure. An AlGaN or GaN single crystalline epitaxial layer is grown on the ultra-thin 2D material interposer by virtue of the van der Waals epitaxy. Therefore, the large-size substrate may be manufactured with far lower costs than related single crystal wafers.

A semiconductor structure comprises a layer of a first III-nitride material having a first lattice dimension; a non-porous layer of a second III-nitride material having a second lattice dimension different from the first lattice dimension; and a porous region of III-nitride material disposed between the layer of first III-nitride material and the non-porous layer of the second III-nitride material. An optoelectronic semiconductor device, an LED, and a method of manufacturing a semiconductor structure are also provided.

Disclosed is a method of facilitating straining of a semiconductor element (331) for semiconductor fabrication. In a described embodiment, the method comprises: providing a base layer (320) with the semiconductor element (331) arranged on a first base portion (321) of the base layer (320), the semiconductor element (331) being subjected to a strain relating to a characteristic of the first base portion (321); and adjusting the characteristic of the first base portion (321) to facilitate straining of the semiconductor element (331).

This disclosure relates to the field of display technologies and, in particular to a thin film packaging structure and a display panel. A thin film packaging structure includes a first inorganic packaging layer for covering a device to be packaged; an organic packaging layer formed at a side of the first inorganic packaging layer; a second inorganic packaging layer formed at a side of the organic packaging layer facing away from the first inorganic packaging layer; and at least one first inorganic adjusting layer formed at a side of the first inorganic packaging layer facing away from the device to be packaged. The at least one first inorganic adjusting layer has an elasticity modulus greater than that of the first inorganic packaging layer or the second inorganic packaging layer.

This disclosure relates to the field of display technologies and, in particular to a thin film packaging structure and a display panel. A thin film packaging structure includes a first inorganic packaging layer for covering a device to be packaged; an organic packaging layer formed at a side of the first inorganic packaging layer; a second inorganic packaging layer formed at a side of the organic packaging layer facing away from the first inorganic packaging layer; and at least one first inorganic adjusting layer formed at a side of the first inorganic packaging layer facing away from the device to be packaged. The at least one first inorganic adjusting layer has an elasticity modulus greater than that of the first inorganic packaging layer or the second inorganic packaging layer.

A method for making a device. The method comprises forming a buffer layer on a substrate; forming a periodically doped layer on the buffer layer; forming one or more wires on the periodically doped layer, the wires being chosen from nanowires and microwires; and introducing porosity into the periodically doped layer to form a porous distributed Bragg reflector (DBR). Various devices that can be made by the method are also disclosed.

A method for making a device. The method comprises forming a buffer layer on a substrate; forming a periodically doped layer on the buffer layer; forming one or more wires on the periodically doped layer, the wires being chosen from nanowires and microwires; and introducing porosity into the periodically doped layer to form a porous distributed Bragg reflector (DBR). Various devices that can be made by the method are also disclosed.

An epitaxial structure includes a quantum well structure, a first type semiconductor layer, and a second type semiconductor layer. The quantum well structure has an upper surface and a lower surface opposite to each other and includes at least one quantum well layer and at least one quantum barrier layer stacked alternately. The quantum well layer includes at least one patterned layer, and the patterned layer includes multiple geometric patterns. The first type semiconductor layer is disposed on the lower surface of the quantum well structure. The second type semiconductor layer is disposed on the upper surface of the quantum well structure.