This technology provides an electronic device and a method of fabricating the same. An electronic device in accordance with an implementation of this document includes a transistor comprising a semiconductor substrate including an active region defined by an isolation layer; and a gate which is formed over the active region and the isolation layer and extends in a first direction to cross the active region, wherein the active region includes a head portion towering over the isolation layer, a body portion disposed under the head portion, and a neck portion which is disposed between the head portion and the body portion and is recessed compared to the head portion and the body portion in the first direction, in a region where the gate and the active region overlap with each other.

An ultra-high-density vertical cross-point array comprises a plurality of horizontal line layers having horizontal lines interleaved with a plurality of vertical lines arranged in rows and columns. The vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each consecutive pair of horizontal lines in each horizontal line layer. Each vertical line comprises a center conductor surrounded by a single or multi-layered memory film. Accordingly, when interleaved with the horizontal lines, two-terminal memory cells are integrally formed between the center conductor of each vertical line and each crossing horizontal line. By configuring the vertical and horizontal lines so that a row of vertical lines is positioned between each consecutive pair of horizontal lines, a unit memory cell footprint of just 2F.sup.2 may be realized.

A semiconductor device includes a first electrode and a first carbon layer on the first electrode. A switch layer is disposed on the first carbon layer and a second carbon layer is disposed on the switch layer. At least one tunneling oxide layer is disposed between the first carbon layer and the second carbon layer. The device further includes a second electrode on the second carbon layer.

An analog Magnetoresistive Random Access Memory (MRAM) cell is provided. The analog MRAM cell includes a magnetic free layer having a first domain having a first magnetization direction, a second domain having a second magnetization direction opposite to the first magnetization direction and a domain wall located between the first domain and the second domain. The analog MRAM cell further includes a magnetically pinned layer. The analog MRAM cell also includes an insulating tunnel barrier between the magnetic free layer and the magnetically pinned layer. The analog MRAM cell additionally includes an electrode located adjacent to the magnetic free layer configured to generate heat by supplying current to decrease a conductance of the magnetic free layer.

A variable resistance memory device includes memory cells arranged on a substrate and an insulating structure between the memory cells. Each of the memory cells includes a variable resistance pattern and a switching pattern vertically stacked on the substrate. The insulating structure includes a first insulating pattern between the memory cells, and a second insulating pattern between the first insulating pattern and each of the memory cells. The first insulating pattern includes a material different from a material of the second insulating pattern.

Technologies relating to a crossbar array circuit with a one-transistor-two-memristor (1T2R) Resistive Random-Access Memory (RRAM) and a common reactive electrode in the applications of the crossbar array circuit are disclosed. An example crossbar array circuit includes: a two-memristor structure, wherein the two-memristor structure includes: a first bottom electrode; a first RRAM stack formed on the first bottom electrode; a top electrode formed on the first RRAM stack; a second RRAM stack formed on the top electrode; and a second bottom electrode formed on the second RRAM stack, wherein the top electrode is a reactive or scavenging electrode which is configured to provide the first RRAM stack and the second RRAM stack with oxygen vacancies near the reactive electrode; and a one-transistor structure, wherein the one-transistor structure includes: a source electrode; a gate electrode; and a drain electrode, wherein the source electrode is connected to the top electrode.

A method of forming a metal chalcogenide material. The method comprises introducing a metal precursor and a chalcogenide precursor into a chamber, and reacting the metal precursor and the chalcogenide precursor to form a metal chalcogenide material on a substrate. The metal precursor is a carboxylate of an alkali metal, an alkaline earth metal, a transition metal, a post-transition metal, or a metalloid. The chalcogenide precursor is a hydride, alkyl, or aryl precursor of sulfur, selenium, or tellurium or a silylhydride, silylalkyl, or silylaryl precursor of sulfur, selenium, or tellurium. Methods of forming a memory cell including the metal chalcogenide material are also disclosed, as are memory cells including the metal chalcogenide material.

One embodiment of the invention includes a reconfigurable circuit comprising a phase-change material switch. The phase-change material switch includes an actuation portion configured to receive a control signal having one of a first state and a second state and to emit a first heat profile in response to the first state of the control signal and a second heat profile in response to the second state of the control signal. The phase-change material switch also includes a switch portion comprising a phase-change material in proximity with the actuation portion. The switch portion can be selectable between a conducting state in response to the first heat profile to conduct an input signal from an input to an output of the phase-change material switch and a blocking state in response to the second heat profile to substantially block the input signal from the input to the output.

A semiconductor device includes first isolation lines positioned above a substrate and extending in a first direction. Second isolation lines are positioned above the first isolation lines and extend in a second direction, perpendicular to the first direction, to have a right angle on a plane parallel to an upper surface of the substrate. A first conductive line is disposed between the first isolation lines. The first conductive line is spaced apart from the substrate. A second conductive line is disposed between the second isolation lines. First data storage patterns are disposed between the first isolation lines. The first data storage patterns are positioned above the first conductive line. Second data storage patterns are disposed between the second isolation lines. The second data storage patterns are positioned above the second conductive line. A third conductive line is positioned above the second isolation lines and extends in the first direction.

An electronic device includes a semiconductor memory that includes: a variable resistance element formed over a substrate; and a carbon-containing aluminum nitride layer formed on sidewalls and in an upper portion of the variable resistance element.