A structure of transmission line includes a first transmission line, a second transmission line and an interlayer via. The first transmission line includes a first line segment, a second segment and a first signal via. The second transmission line includes a third line segment, a fourth segment and a second signal via. Both of the first line segment and the third line segment are disposed in a first signal transmission layer and extend along a first direction. Both of the second line segment and the fourth line segment are disposed in a second signal transmission layer and extend along a second direction. The first signal via is connected to the first line segment and the second line segment. The second signal via is connected to the third line segment and the fourth line segment. The interlayer via is adjacent to the first line segment or the second line segment.

A passive circulator utilizing sequentially-switched delay lines (SSDL) in which delay line sections are sequentially turned on and off to achieve non-reciprocity to provide rejection/separations between different signals at the same/similar frequency, such as between a transmitted and received signal. The circulator is well-suited for on-chip integration and can be utilized across a wide frequency range. Various embodiments are described for separating signal waveforms.

A transmission line is provided with a fixed physical length and a programmable electrical length for achieving a programmable time delay. The transmission line can include a dielectric and a biasing device disposed across the dielectric, and the biasing device can dynamically and continuously vary an absolute level of a bias voltage across the dielectric to vary a dielectric constant of the dielectric, which can vary a time delay of the transmission line. In some embodiments, the biasing device can modulate the bias voltage from a positive voltage to a negative voltage at a frequency and with waveform characteristics that prevent such modulation from interfering with a signal propagating through the dielectric, that prevent the bias voltage from unintentionally varying the time delay of the transmission line when the absolute level of the bias voltage is constant, and that prevents ion impurities within the dielectric from accumulating on bias electrodes.

A package trace design technique provides at least partial cancelation of reflections. In one illustrative method of providing a high-bandwidth chip-to-chip link with a first die coupled to a second die via a first substrate trace, an intermediate trace, and a second substrate trace, the method includes: (a) determining a first propagation delay for an electrical signal to traverse the first substrate trace, the electrical signal having a predetermined symbol interval; (b) determining a second propagation delay for the electrical signal to traverse the second substrate trace; and (c) setting a length for at least one of the first and second substrate traces, the length yielding a difference between the first and second propagation delays, the difference having a magnitude equal to half the predetermined symbol interval.

A transmission line is provided with a fixed physical length and a programmable electrical length for achieving a programmable time delay. The transmission line can include a dielectric and a biasing device disposed across the dielectric, and the biasing device can dynamically and continuously vary an absolute level of a bias voltage across the dielectric to vary a dielectric constant of the dielectric, which can vary a time delay of the transmission line. In some embodiments, the biasing device can modulate the bias voltage from a positive voltage to a negative voltage at a frequency and with waveform characteristics that prevent such modulation from interfering with a signal propagating through the dielectric, that prevent the bias voltage from unintentionally varying the time delay of the transmission line when the absolute level of the bias voltage is constant, and that prevents ion impurities within the dielectric from accumulating on bias electrodes.

A package trace design technique provides at least partial cancelation of reflections. In one illustrative method of providing a high-bandwidth chip-to-chip link with a first die coupled to a second die via a first substrate trace, an intermediate trace, and a second substrate trace, the method includes: (a) determining a first propagation delay for an electrical signal to traverse the first substrate trace, the electrical signal having a predetermined symbol interval; (b) determining a second propagation delay for the electrical signal to traverse the second substrate trace; and (c) setting a length for at least one of the first and second substrate traces, the length yielding a difference between the first and second propagation delays, the difference having a magnitude equal to half the predetermined symbol interval.

A transmission line is provided with a fixed physical length and a programmable electrical length for achieving a programmable time delay. The transmission line can include a dielectric and a biasing device disposed across the dielectric, and the biasing device can dynamically and continuously vary an absolute level of a bias voltage across the dielectric to vary a dielectric constant of the dielectric, which can vary a time delay of the transmission line. In some embodiments, the biasing device can modulate the bias voltage from a positive voltage to a negative voltage at a frequency and with waveform characteristics that prevent such modulation from interfering with a signal propagating through the dielectric, that prevent the bias voltage from unintentionally varying the time delay of the transmission line when the absolute level of the bias voltage is constant, and that prevents ion impurities within the dielectric from accumulating on bias electrodes.

A structure of transmission line includes a first transmission line, a second transmission line and an interlayer via. The first transmission line includes a first line segment, a second segment and a first signal via. The second transmission line includes a third line segment, a fourth segment and a second signal via. Both of the first line segment and the third line segment are disposed in a first signal transmission layer and extend along a first direction. Both of the second line segment and the fourth line segment are disposed in a second signal transmission layer and extend along a second direction. The first signal via is connected to the first line segment and the second line segment. The second signal via is connected to the third line segment and the fourth line segment. The interlayer via is adjacent to the first line segment or the second line segment.

A switchless combiner includes a circuit having a delay line consisting of a constant-impedance transmission line and a device adapted to vary the electric length of said transmission line, the device including a metallic body with walls defining a cavity, the walls being interrupted to define a slot, the cavity and the slot extending along at least a portion of the length of the device, the cavity including a first portion having a first cross-section and a second portion having a second cross-section which is greater than the first cross-section, the second portion having a dielectric element with a cutout corresponding to the slot, the first and second portions extending in the longitudinal direction of the device and the transmission line being positioned, inside the first and second portion, in the cutout, the dielectric element occupying the cavity of the second portion, and having an element to translate the dielectric element on the circuit in the longitudinal direction of the device.