A VCSEL device includes a first electrical contact, a substrate, a second electrical contact, and an optical resonator arranged on a first side of the substrate. The optical resonator includes a first reflecting structure comprising a first distributed Bragg reflector, a second reflecting structure comprising a second distributed Bragg reflector, an active layer arranged between the first and second reflecting structures, and a guiding structure. The guiding structure is configured to define a first relative intensity maximum of an intensity distribution within the active layer at a first lateral position such that a first light emitting area is provided, to define at least a second relative intensity maximum of the intensity distribution within the active layer at a second lateral position such that a second light emitting area is provided, and to reduce an intensity in between the at least two light-emitting areas during operation.

A semiconductor device having a GeSiSn base region combined with an emitter region and a collector region can be used to fabricate a bipolar transistor or a heterojunction bipolar transistor. The GeSiSn base region can be compositionally graded or latticed matched or strained to GaAs. The GeSiSn base region can be wafer bonded to a GaN or SiC collector region.

The present disclosure provides a narrow-pulse-width pulse laser, including a circuit substrate, a laser chip, one or more capacitors, and a field effect transistor. Each of the field effect transistor, the capacitor, and the laser chip is electrically connected to the circuit substrate. The capacitors are arranged between the field effect transistor and the laser chip along an extension direction of a gap between the field effect transistor and the laser chip. The circuit substrate may include a first conductor layer; a second conductor layer; and an insulating layer arranged between the first conductor layer and the second conductor layer, wherein the first conductor layer and the second conductor layer are electrically connected through a via hole in the insulating layer.

A vertical cavity surface emitting laser (VCSEL) has first and second electrical contacts, and an optical resonator. The optical resonator has first and second distributed Bragg reflectors (DBRs), an active layer, a distributed heterojunction bipolar phototransistor (DHBP), and an optical guide. The DHBP has a collector layer, light sensitive layer; a base layer; and an emitter layer. There is an optical coupling between the active layer and the DHBP for providing an active carrier confinement by the DHBP. The optical guide guides an optical mode within the optical resonator during operation. The optical guide is outside a current flow which can be provided by the first and second electrical contacts during operation of the VCSEL. The optical guide is outside a layer sequence between the first and second electrical contacts in the vertical direction of the VCSEL. The optical guide has an oxide aperture arranged in the second DBR.

Integrated circuitry is fabricated from semiconductor layers formed on a substrate, which include at least one n-type layer, an inverted p-type modulation doped quantum well (mod-doped QW) structure, a non-inverted n-type mod-doped QW structure, and at least one p-type layer including a first P+-type layer formed below a second P-type layer. An etch operation exposes the second p-type layer. P-type ions are implanted into the exposed second p-type layer. A gate electrode of a n-channel HFET device is formed in contact with the p-type ion implanted region. Source and drain electrodes of the n-channel HFET device are formed in contact with n-type ion implanted regions formed in contact with the n-type mod-doped QW structure. P-channel HFET devices, complementary BICFET devices, stacked complementary HFET devices and circuits and/or logic gates based thereon, and a variety of optoelectronic devices and optical devices can also be formed as part of the integrated circuitry.

The present disclosure provides a narrow-pulse-width pulse laser, including a circuit substrate, a laser chip, one or more capacitors, and a field effect transistor. Each of the field effect transistor, the capacitor, and the laser chip is electrically connected to the circuit substrate. The capacitors are arranged between the field effect transistor and the laser chip along an extension direction of a gap between the field effect transistor and the laser chip. The circuit substrate may include a first conductor layer; a second conductor layer; and an insulating layer arranged between the first conductor layer and the second conductor layer, wherein the first conductor layer and the second conductor layer are electrically connected through a via hole in the insulating layer.

A method of forming an integrated circuit employs a plurality of layers formed on a substrate including i) bottom n-type ohmic contact layer, ii) p-type modulation doped quantum well structure (MDQWS) with a p-type charge sheet formed above the bottom n-type ohmic contact layer, iii) n-type MDQWS offset vertically above the p-type MDQWS, and iv) etch stop layer formed above the p-type MDQWS. P-type ions are implanted to define source/drain ion-implanted contact regions of a p-channel HFET which encompass the p-type MDQWS. An etch operation removes layers above the etch stop layer of iv) for the source/drain ion-implanted contact regions using an etchant that automatically stops at the etch stop layer of iv). Another etch operation removes remaining portions of the etch stop layer of iv) to form mesas that define an interface to the source/drain ion-implanted contact regions of the p-channel HFET. Source/Drain electrodes are on such mesas.

A solid-state light source with built-in access resistance modulation is described. The light source can include an active region configured to emit electromagnetic radiation during operation of the light source. The active region can be formed at a p-n junction of a p-type side with a p-type contact and a n-type side with a n-type contact. The light source includes a control electrode configured to modulate an access resistance of an access region located on the p-type side and/or an access resistance of an access region located on the n-type side of the active region. The solid-state light source can be implemented in a circuit, which includes a voltage source that supplies a modulation voltage to the control electrode to modulate the access resistance(s).

The methods of manufacture of GeSiSn heterojunction bipolar transistors, which include light emitting transistors and transistor lasers and photo-transistors and their related structures are described herein. Other embodiments are also disclosed herein.

A structure for impedance signal lines of a transistor outline (TO)-can type semiconductor package is disclosed. The TO-can type semiconductor package may include a header including a semiconductor laser diode disposed on one side thereof; a signal line penetrating the header and including a one end protruding from the one side of the header; and an edge-coupled microstrip (ECM) portion connected to the signal line. The ECM portion is configured to include a dielectric and ECM lines are formed as conductive patterns having predetermined widths and leaving a predetermined space therebetween on a first side of the dielectric, and respectively connected to the signal lines.