A vertical cavity light-emitting element includes a substrate, a first multilayer reflector, a semiconductor structure layer, an electrode layer, and a second multilayer reflector. The semiconductor structure layer includes a first semiconductor layer of a first conductivity type on the first multilayer reflector, a light-emitting layer on the first semiconductor layer, and a second semiconductor layer of a second conductivity type on the light-emitting layer. The electrode layer is on an upper surface of the semiconductor structure layer and is electrically in contact with the second semiconductor layer in one region of the upper surface. The second multilayer reflector covers the one region on the electrode layer and constitutes a resonator with the first multilayer reflector. The semiconductor structure layer has one recessed structure including one or a plurality of recessed portions passing through the light-emitting from the upper surface in a region surrounding the one region.

A vertical cavity surface emitting laser (VCSEL) may include an active region (e.g., one or more quantum wells) and a chirped pattern reflector. The active region may be configured to be electrically pumped such that the active region generates light having a fundamental mode and a higher order mode. The chirped pattern reflector may include a first portion presenting to the active region as a first portion of an effective mirror having a concave shape and a second portion presenting to the active region as a second portion of the effective mirror having a convex shape.

A semiconductor component for emitting light includes a main body that comprises at least one mesa body. The mesa body has an emission region for emitting the light. The emission region is assigned a first mirror portion, a second mirror portion, and an active portion arranged between the two mirror portions and serving to produce the light. The semiconductor component further includes electrical contacts for feeding electrical energy into the active portion, with at least one stress element that is attached to a surface of the main body. The stress element is configured to generate in the main body a material stress which has an effect on one or more polarization properties of the emitted light.

A plurality of surface emitting lasers are formed on the single surface emitting laser element. The plurality of surface emitting lasers have respective emission wavelengths selected from wavelengths satisfying condition of:
0<λ.sub.1−λ.sub.s≤5.36×10.sup.−5λ.sub.c.sup.2−×5.83×10.sup.−2λ.sub.c+32.4 where a first emission wavelength is λ.sub.1 [nm], a second emission wavelength shorter than the first emission wavelength is λ.sub.s [nm], and a middle wavelength between the first emission wavelength and the second emission wavelength is λ.sub.c [nm]. At least one of the plurality of surface emitting lasers has an emission wavelength different from an emission wavelength of another surface emitting laser.

Methods for forming an at least partially oxidized confinement layer of a semiconductor device and corresponding semiconductor devices are provided. The method comprises forming two or more layers of a semiconductor device on a substrate. The layers include an exposed layer and a to-be-oxidized layer. The to-be-oxidized layer is disposed between the substrate and the exposed layer. The method further comprises etching, using a masking process, a pattern of holes that extend through the exposed layer at least to a first surface of the to-be-oxidized layer. Each hole of the pattern of holes extends in a direction that is transverse to a level plane that is parallel to the first surface of the to-be-oxidized layer. The method further comprises oxidizing the to-be-oxidized layer through the pattern of holes by exposing the two or more layers of the semiconductor device to an oxidizing gas to form a confinement layer.

A semiconductor structure comprising a matrix having a first cubic Group-III nitride with a first band gap, and a second cubic Group-III nitride having a second band gap and forming a region embedded within the matrix. The second cubic Group-III nitride comprises an alloying material which reduces the second band gap relative to the first band gap, a quantum wire is defined by a portion within the region embedded within the matrix, the portion forming a one-dimensional charge-carrier confinement channel, wherein the quantum wire is operable to exhibit emission luminescence which is optically polarised.

An on-chip miniarray of optically-coupled oxide-confined apertures of vertical cavity surface emitting lasers (VCSELs) is realized by etching holes from the chip surface down to at least one aperture layer. Oxidation of the aperture layer results in electrically-isolated apertures suitable for current injection. The lateral distance between the aperture centers and the shape of the aperture is chosen to result in effective interaction of the neighboring optical modes in the related aperture regions through optical field coupling effect causing the interaction-induced splitting of the wavelengths of the optical modes. At least one aperture has a different surface area due to different spacing of the etched holes. Different aperture sizes result in different wavelengths of the coupled modes. Splitting of the cavity modes in a frequency domain 3-100 GHz extends the modulation bandwidth of the device due to photon-photon interaction effects.

Selective deposition of highly reflective coating and/or anti-reflecting coating over apertures of different VCSELs foiining a miniarray allows stabilizing lasing in a single coherent mode of the array. Most preferably, highly reflective coating covers the largest aperture and stabilizes the fundamental mode of the coherent array. Anti-reflecting coatings can be deposited on at least one other aperture to reduce the photon lifetime and increase the homogeneous broadening of the related resonant wavelength. Consequently broadening of the photon-photon interaction resonances between the cavity modes can be controlled. Such resonance broadening allows control over the shape of the current modulation curve of the miniarray of VCSELs with the frequency maximum defined by the splitting of the cavity modes and the broadening defined by the broadening of the photon resonances. An increase in −3dB modulation bandwidth of the VCSEL miniarray up to at least 70 GHz is possible.

Such miniarray of VCSELs enables efficient coupling of the emitted light to a multimode optical fiber with the efficiency of at least 70%.

A MEMS tunable VCSEL includes a membrane device having a mirror and a distal-side electrostatic cavity for displacing the mirror to increase a size of an optical cavity. A VCSEL device includes an active region for amplifying light. Then, a proximal-side electrostatic cavity is defined between the VCSEL device and the membrane device is used to displace the mirror to decrease a size of an optical cavity.

A method of incorporating a control structure within a VCSEL device cavity using a multiphase growth sequence includes forming a first mirror over a substrate, forming an active region over the first mirror, forming a spacer on a surface of the active region, forming a control structure on a surface of the spacer, and forming a second mirror over the control structure. The active region and the spacer are formed using a molecular beam epitaxy (MBE) process during an MBE phase of the multiphase growth sequence. The second mirror is formed using a metal-organic chemical vapor deposition (MOCVD) process during an MOCVD phase of the multiphase growth sequence. The control structure is formed using a chemical etching process during a transition period between the MBE phase and the MOCVD phase of the multiphase growth sequence.

An optoelectronic device includes a base chip, including a silicon die having a photodiode disposed at its front surface and a first anode contact and a first cathode contact disposed on the front surface. A laser diode driver circuit on the silicon die supplies an electrical drive signal between the first anode contact and the first cathode contact. An emitter chip includes a III-V semiconductor die, which is mounted with its front side facing toward the front surface of the silicon die. A second anode contact and a second cathode contact are disposed on the front side of the III-V semiconductor die in electrical communication with the first anode contact and the first cathode contact. A VCSEL is disposed on the front side of the III-V semiconductor die in coaxial alignment with the photodiode and receives the drive signal from the second anode contact and the second cathode contact.