Patent classifications
H01S5/18372
Vertical-cavity surface-emitting laser with a tunnel junction
A VCSEL may include an n-type substrate layer and an n-type bottom mirror on a surface of the n-type substrate layer. The VCSEL may include an active region on the n-type bottom mirror and a p-type layer on the active region. The VCSEL may include an oxidation layer over the active region to provide optical and electrical confinement of the VCSEL. The VCSEL may include a tunnel junction over the p-type layer to reverse a carrier type of an n-type top mirror. Either the oxidation layer is on or in the p-type layer and the tunnel junction is on the oxidation layer, or the tunnel junction is on the p-type layer and the oxidation layer is on the tunnel junction. The VCSEL may include the n-type top mirror over the tunnel junction, a top contact layer over the n-type top mirror, and a top metal on the top contact layer.
SEMICONDUCTOR INTEGRATED CIRCUIT AND METHODOLOGY FOR MAKING SAME
Integrated circuitry is fabricated from semiconductor layers formed on a substrate, which include at least one n-type layer, an inverted p-type modulation doped quantum well (mod-doped QW) structure, a non-inverted n-type mod-doped QW structure, and at least one p-type layer including a first P+-type layer formed below a second P-type layer. An etch operation exposes the second p-type layer. P-type ions are implanted into the exposed second p-type layer. A gate electrode of a n-channel HFET device is formed in contact with the p-type ion implanted region. Source and drain electrodes of the n-channel HFET device are formed in contact with n-type ion implanted regions formed in contact with the n-type mod-doped QW structure. P-channel HFET devices, complementary BICFET devices, stacked complementary HFET devices and circuits and/or logic gates based thereon, and a variety of optoelectronic devices and optical devices can also be formed as part of the integrated circuitry.
VERTICAL-CAVITY SURFACE-EMITTING LASER AND METHOD FOR FORMING THE SAME
A vertical cavity surface emitting laser includes an active area, an inner trench, an outer trench, and a first implantation region. The active area includes a first mirror, an active region, a second mirror, and an etch stop layer. The first mirror is formed over a substrate. The active region is formed over the first mirror. The second mirror is formed over the active region. The etch stop layer with an aperture is formed between the active region and the second mirror. The inner trench surrounds the active area in a top view. The outer trench if formed beside the inner trench. The first implantation region is formed below the inner trench.
Widely tunable swept source
A high-speed, single-mode, high power, reliable and manufacturable wavelength-tunable light source operative to emit wavelength tunable radiation over a wavelength range contained in a wavelength span between about 950 nm and about 1150 nm, including a vertical cavity laser (VCL), the VCL having a gain region with at least one compressively strained quantum well containing Indium, Gallium, and Arsenic.
WIDELY TUNABLE SHORT CAVITY LASER
A tunable source includes a short-cavity laser optimized for performance and reliability in SSOCT imaging systems, spectroscopic detection systems, and other types of detection and sensing systems. The short cavity laser has a large free spectral range cavity, fast tuning response and single transverse, longitudinal and polarization mode operation, and includes embodiments for fast and wide tuning, and optimized spectral shaping. Disclosed are both electrical and optical pumping in a MEMS-VCSEL geometry with mirror and gain regions optimized for wide tuning, high output power, and a variety of preferred wavelength ranges; and a semiconductor optical amplifier, combined with the short-cavity laser to produce high-power, spectrally shaped operation. Several preferred imaging and detection systems make use of this tunable source for optimized operation are also disclosed.
VERTICAL-CAVITY SURFACE-EMITTING LASER WITH A TUNNEL JUNCTION
A VCSEL may include an n-type substrate layer and an n-type bottom mirror on a surface of the n-type substrate layer. The VCSEL may include an active region on the n-type bottom mirror and a p-type layer on the active region. The VCSEL may include an oxidation layer over the active region to provide optical and electrical confinement of the VCSEL. The VCSEL may include a tunnel junction over the p-type layer to reverse a carrier type of an n-type top mirror. Either the oxidation layer is on or in the p-type layer and the tunnel junction is on the oxidation layer, or the tunnel junction is on the p-type layer and the oxidation layer is on the tunnel junction. The VCSEL may include the n-type top mirror over the tunnel junction, a top contact layer over the n-type top mirror, and a top metal on the top contact layer.
Widely tunable short-cavity laser
A tunable source includes a short-cavity laser optimized for performance and reliability in SSOCT imaging systems, spectroscopic detection systems, and other types of detection and sensing systems. The short cavity laser has a large free spectral range cavity, fast tuning response and single transverse, longitudinal and polarization mode operation, and includes embodiments for fast and wide tuning, and optimized spectral shaping. Disclosed are both electrical and optical pumping in a MEMS-VCSEL geometry with mirror and gain regions optimized for wide tuning, high output power, and a variety of preferred wavelength ranges; and a semiconductor optical amplifier, combined with the short-cavity laser to produce high-power, spectrally shaped operation. Several preferred imaging and detection systems make use of this tunable source for optimized operation are also disclosed.
Semiconductor integrated circuit and methodology for making same
Integrated circuitry is fabricated from semiconductor layers formed on a substrate, which include at least one n-type layer, an inverted p-type modulation doped quantum well (mod-doped QW) structure, a non-inverted n-type mod-doped QW structure, and at least one p-type layer including a first P+-type layer formed below a second P-type layer. An etch operation exposes the second p-type layer. P-type ions are implanted into the exposed second p-type layer. A gate electrode of a n-channel HFET device is formed in contact with the p-type ion implanted region. Source and drain electrodes of the n-channel HFET device are formed in contact with n-type ion implanted regions formed in contact with the n-type mod-doped QW structure. P-channel HFET devices, complementary BICFET devices, stacked complementary HFET devices and circuits and/or logic gates based thereon, and a variety of optoelectronic devices and optical devices can also be formed as part of the integrated circuitry.
Surface emitting laser
A surface emitting laser includes a substrate, a lower contact layer disposed on the substrate, a semiconductor layer mesa including a lower reflector layer, an active layer, an upper reflector layer, and an upper contact layer which are laminated, in the order named, on the lower contact layer, an annular electrode disposed on the upper contact layer, and a light transmitting window situated inside the annular electrode to transmit laser light, wherein the upper reflector layer includes a first region and a second region, the first region being inclusive of an area situated directly below the electrode and the light transmitting window, the second region being inclusive of an area outside the mesa and inclusive of a surrounding area of the first region within the mesa, and wherein a proton concentration in the first region is lower than a proton concentration in the second region.
SEMICONDUCTOR INTEGRATED CIRCUIT AND METHODOLOGY FOR MAKING SAME
Integrated circuitry is fabricated from semiconductor layers formed on a substrate, which include at least one n-type layer, an inverted p-type modulation doped quantum well (mod-doped QW) structure, a non-inverted n-type mod-doped QW structure, and at least one p-type layer including a first P+-type layer formed below a second P-type layer. An etch operation exposes the second p-type layer. P-type ions are implanted into the exposed second p-type layer. A gate electrode of a n-channel HFET device is formed in contact with the p-type ion implanted region. Source and drain electrodes of the n-channel HFET device are formed in contact with n-type ion implanted regions formed in contact with the n-type mod-doped QW structure. P-channel HFET devices, complementary BICFET devices, stacked complementary HFET devices and circuits and/or logic gates based thereon, and a variety of optoelectronic devices and optical devices can also be formed as part of the integrated circuitry.