Patent classifications
H01S5/30
METHOD FOR MANUFACTURING OPTICAL SEMICONDUCTOR DEVICE
Provided here are: a mesa strip which has an n-type cladding layer, an active layer and a p-type cladding layer that are stacked sequentially on a surface of an n-type substrate; Fe-doped semi-insulating layers which are embedded along both sides of the mesa stripe, each up to a height higher than the mesa stripe; n-type blocking layers which are stacked on respective surfaces of the Fe-doped semi-insulating layers located on the both sides of the mesa stripe, and which are spaced apart from each other with an interval that is a space corresponding to a central portion of the active layer and is thus narrower than the active layer; p-type cladding layers which are formed on back surfaces of respective mesa-stripe-side end portions of the n-type blocking layers; and a p-type cladding layer which buries a top of the mesa stripe, the p-type cladding layers and the n-type blocking layers.
EPITAXIAL SUBSTRATE WITH 2D MATERIAL INTERPOSER, MANUFACTURING METHOD, AND MANUFACTURING ASSEMBLY
Disclosed is an epitaxial substrate with a 2D material interposer on a surface of a polycrystalline substrate. The ultra-thin 2D material interposer is grown by van der Waals epitaxy. The lattice constant of a surface layer of the ultra-thin 2D material interposer and the coefficient of thermal expansion of the substrate base are highly fit with those of AlGaN or GaN. The ultra-thin 2D material interposer is of a single-layer structure or a composite-layer structure. An AlGaN or GaN single crystalline epitaxial layer is grown on the ultra-thin 2D material interposer by virtue of the van der Waals epitaxy. Therefore, the large-size substrate may be manufactured with far lower costs than related single crystal wafers.
VERTICAL CAVITY LIGHT-EMITTING ELEMENT
A vertical cavity light-emitting element includes a substrate, a first multilayer reflector, a semiconductor structure layer, an electrode layer, and a second multilayer reflector. The semiconductor structure layer includes a first semiconductor layer of a first conductivity type on the first multilayer reflector, a light-emitting layer on the first semiconductor layer, and a second semiconductor layer of a second conductivity type on the light-emitting layer. The electrode layer is on an upper surface of the semiconductor structure layer and is electrically in contact with the second semiconductor layer in one region of the upper surface. The second multilayer reflector covers the one region on the electrode layer and constitutes a resonator with the first multilayer reflector. The semiconductor structure layer has one recessed structure including one or a plurality of recessed portions passing through the light-emitting from the upper surface in a region surrounding the one region.
SEMICONDUCTOR LASER SOURCE
A semiconductor laser source includes a structured layer formed on a substrate made of silicon and having an upper face. The structured layer includes a passive optical component chosen from the group composed of an optical reflector and a waveguide. The component is encapsulated in silica or produced on a silica layer. At least one pad extends from a lower face of the structured layer, making direct contact with the substrate made of silicon, to an upper face flush with the upper face of the structured layer. The pad is produced entirely from silicon nitride, in order to form a thermal bridge through the structured layer. An optical amplifier is bonded directly above the passive optical component and partially to the upper face of the pad in order to dissipate the heat that it generates to the substrate made of silicon.
SILICON PHOTONIC CHIP WITH INTEGRATED ELECTRO-OPTICAL COMPONENT AND LENS ELEMENT
Embodiments include a silicon photonic chip having a substrate, an optical waveguide on a surface of the substrate and a cavity. The cavity includes an electro-optical component, configured for emitting light perpendicular to said surface and a lens element arranged on top of the electro-optical component. The lens is configured for collimating light emitted by the electro-optical component. The chip also includes a deflector arranged on top of the lens element and configured for deflecting light collimated through the latter toward the optical waveguide. The lens element includes electrical conductors connected to the electro-optical component. The electrical conductors of the lens element may for instance include one or more through vias, one or more bottom electrical lines on a bottom side of the lens element (facing the electro-optical component), and at least one top electrical line.
RARE EARTH INTERLAYS FOR MECHANICALLY LAYERING DISSIMILAR SEMICONDUCTOR WAFERS
Structures described herein may include mechanically bonded interlayers for formation between a first Group III-V semiconductor layer and a second semiconductor layer. The mechanically bonded interlayers provide reduced lattice strain by strain balancing between the Group III-V semiconductor layer and the second semiconductor layer, which may be silicon.
BURIED HETEROSTRUCTURE SEMICONDUCTOR OPTICAL AMPLIFIER AND METHOD FOR FABRICATING THE SAME
A method for fabricating a buried heterostructure semiconductor optical amplifier is provided. The method includes a step providing a patterned dielectric layer on a substrate, the patterned dielectric layer having openings to expose uncovered regions of the substrate. The method also includes, in a single metal organic chemical vapour deposition (MOCVD) run: etching the uncovered regions of the substrate to form angles at corresponding edges thereof and diffusing a p-dopant in the substrate to obtain a p-dopant distribution in a portion of the substrate; etching a portion of the p-dopant thereby defining a recess in the substrate and growing a n-blocking layer in the recess; sequentially growing, over a portion of the n-blocking layer, an active region, a p-overclad, a p-contact, and a p-metal contact; and growing a n-metal contact on a backside of the substrate. The single MOCVD run combines selective area growth, p-dopant diffusion and etching techniques.
Radiation-emitting semiconductor component
A radiation-emitting semiconductor component is disclosed. In an embodiment, a component includes a semiconductor layer sequence and a carrier on which the semiconductor layer sequence is arranged, wherein the semiconductor layer sequence comprises an active region configured for generating radiation, an n-conducting mirror region and a p-conducting mirror region, wherein the active region is arranged between the n-conducting mirror region and the p-conducting mirror region, and wherein the p-conducting mirror region is arranged closer to the carrier than the active region.
SEMICONDUCTOR LASER DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor laser device includes an N-type cladding layer, an active layer, and a P-type cladding layer. The active layer includes a well layer, a P-side first barrier layer above the well layer, and a P-side second barrier layer above the P-side first barrier layer. The P-side second barrier layer has an AI composition ratio higher than an AI composition ratio of the P-side first barrier layer. The P-side second barrier layer has band gap energy greater than band gap energy of the P-side first barrier layer. The semiconductor laser device has an end face window structure in which band gap energy of a portion of the well layer in a vicinity of an end face that emits the laser light is greater than band gap energy of a central portion of the well layer in a resonator length direction.
SURFACE-EMITTING SEMICONDUCTOR LIGHT-EMITTING DEVICE
A surface-emitting semiconductor light-emitting device includes a first semiconductor layers, an active layer on the first semiconductor layer, a photonic crystal layer on the active layer and a second semiconductor layer on the photonic crystal layer. The photonic crystal layer include first protrusions in a first region and second protrusions in a second region. A spacing of adjacent first protrusions is greater than a spacing of adjacent second protrusions. The second semiconductor layer includes a first layer and a second layer on the first layer. The first layer covers first and second protrusions so that a first space remains between the adjacent first protrusions. The first layer includes a first portion provided between the adjacent second protrusions. The second layer includes a second portion provided between the adjacent first protrusions. The first space between the adjacent first protrusions is filled with the second portion of the second layer.