A microcontroller unit for controlling a three-level inverter including delayed fault protection is provided. The microcontroller unit includes an input port configured to receive a trip signal from a fault detection module, and a plurality of EPWM modules, each configured to control a power switch within the three-level inverter. The microcontroller unit includes an auxiliary EPWM module configured to receive the trip signal and produce a delayed trip signal, and processing circuitry coupled with the input port, the plurality of EPWM modules, and the auxiliary EPWM module. The processing circuitry is configured to, in response to activation of the trip signal, direct one of the plurality of EPWM modules to shut off its corresponding power switch upon activation of the trip signal, and to direct a different one of the plurality of EPWM modules to shut off its corresponding power switch upon activation of the delayed trip signal.

A microcontroller unit for controlling a three-level inverter including delayed fault protection is provided. The microcontroller unit includes an input port configured to receive a trip signal from a fault detection module, and a plurality of EPWM modules, each configured to control a power switch within the three-level inverter. The microcontroller unit includes an auxiliary EPWM module configured to receive the trip signal and produce a delayed trip signal, and processing circuitry coupled with the input port, the plurality of EPWM modules, and the auxiliary EPWM module. The processing circuitry is configured to, in response to activation of the trip signal, direct one of the plurality of EPWM modules to shut off its corresponding power switch upon activation of the trip signal, and to direct a different one of the plurality of EPWM modules to shut off its corresponding power switch upon activation of the delayed trip signal.

The present disclosure relates to a solid insulated switch using a semiconductor comprising a main circuit unit connected between systems on both sides thereof, and which has a first semiconductor and a second semiconductor arranged in a series; a snubber circuit having a capacitor and a resistor arranged in a series, one end connected in parallel to the front end of the first semiconductor switch, and the other end connected in parallel to the rear end of the second semiconductor switch; a freewheeling circuit, having a diode and a resistor arranged in a series, one end connected to a common contact between the first semiconductor switch and the second semiconductor switch, and the other end connected to the ground; and a mechanical switch for ensuring physical insulation after fault current interruption.

The present disclosure relates to a solid insulated switch using a semiconductor comprising a main circuit unit connected between systems on both sides thereof, and which has a first semiconductor and a second semiconductor arranged in a series; a snubber circuit having a capacitor and a resistor arranged in a series, one end connected in parallel to the front end of the first semiconductor switch, and the other end connected in parallel to the rear end of the second semiconductor switch; a freewheeling circuit, having a diode and a resistor arranged in a series, one end connected to a common contact between the first semiconductor switch and the second semiconductor switch, and the other end connected to the ground; and a mechanical switch for ensuring physical insulation after fault current interruption.

Digital isolator devices, and many other devices, have a maximum device junction temperature, which, if exceeded, may cause device failure and the integrity of the isolation is no longer guaranteed. The use of an electronic fuse, eFuse, arranged in series with the digital isolator, provides a protection scheme for the digital isolator in which current is limited by the eFuse when it is determined that the supply current of the digital isolator exceeds a predetermined threshold that would the cause junction temperature to increase above an absolute maximum rating. As such, the integrity of the digital isolator is preserved in the event of a system fault.

A circuit breaker distribution system is configured to provide selective coordination. The system comprises a solid-state switch disposed as a main or upstream breaker and a switch with an over current protection disposed as a branch or downstream breaker. The solid-state switch comprises a microcontroller including a processor and a memory, and computer-readable logic code stored in the memory which, when executed by the processor, causes the microcontroller to: allow repeated pulses of current through to the branch or downstream breaker in an event of an overload or short circuit, and choose a maximum current limit for the solid-state switch as a “chop level” such that the chop level is chosen higher than a rated current of the solid-state circuit breaker but low enough that the solid-state switch is not damaged from repeated pulses over a period of time needed to switch OFF the branch or downstream breaker.

A time-admittance fault detection and isolation system includes a series of time-admittance switches spaced apart along the power line, each including a respective time-admittance function. Together, the time-admittance functions define a cascade trip sequence in a downstream-to-upstream direction, which autonomously causes a closest upstream time-admittance switch to a fault to trip to isolate the fault on an upstream side of the fault without communication with the time-admittance switches. The fault detection and isolation system may also include a radio communicating a trip signal from the closest upstream time-admittance switch to the fault to a closest downstream time-admittance switch to the fault. The trip signal causes the closest downstream time-admittance switch to the fault to trip to isolate the fault on a downstream side of the fault. A tie switch closes to back-feed a portion of the electric power line downstream from the closest downstream time-admittance switch to the fault.

A fault isolating device for use in a microgrid disconnected from a main power grid includes a voltage meter for detecting a voltage anomaly indicative of an electrical fault, a timer for establishing a time window that begins and ends a predetermined time after a voltage anomaly is detected, a switch that is opened at the start of the time window, and a microcontroller that determines whether to leave the switch open to isolate a faulted portion of the microgrid or to close the switch. A plurality of fault isolating devices can be distributed throughout a microgrid to isolate a faulted branch or faulted branches of an islanded microgrid without interfering with normal fuse operation when the microgrid is connected to the main power grid.

The present disclosure relates to a recloser control that provides autosynchronization of a microgrid to an area electric power system (EPS). For example, a recloser control may include an output connector that is communicatively coupled to a recloser at a point of common coupling (PCC) between the area EPS and the microgrid. The recloser control may include a processor that acquires a first set of measurements indicating electrical characteristics of the area EPS and acquires a second set of measurements indicating electrical characteristics of the microgrid. The recloser control may send synchronization signals to one or more distributed energy resource (DER) controllers to synchronize one or more DERs to the area EPS based on the first set of measurements and the second set of measurements.

Embodiments of the present disclosure provide an over-voltage protection method, an over-voltage protection device and a display device. When the voltage value of the output signal is greater than the first preset voltage threshold, it is determined whether the voltage value of the output signal meets the preset over-voltage protection condition. If the voltage value of the output signal is detected to meet the preset over-voltage protection condition, the first control signal is output to stop output of the output signal or lower the voltage value of the output signal.