A transformer arrangement includes a transformer having a winding and a surge arrester arrangement connected thereto. The SAA includes a surge arrester (SA) connected across at least a section of the winding and a switch operable between a closed and open state. In the closed state, SA is electrically connected across at least the section, and in the open state, the SA electrically disconnected from at least the section. The SAA includes at least one further SA .sub.arranged to be connected across at least one further section and at least one further switch, operable between a closed and open state, wherein in the closed state the further SA is electrically connected across the at least one further section, and in the open state, the at least one further SA is electrically disconnected from the further section. A method for electrically connecting/disconnecting the transformer to/from the SAA—is also described.

The present disclosure provides an electrostatic discharge (ESD) protection circuit for a chip, including: a monitoring unit, configured to generate a trigger signal when there is an ESD pulse on a power supply pad; a plurality of controllable drive units, connected to the monitoring unit, and each of the controllable drive units being configured to switch an operating state under a control of a control signal, wherein the operating state includes an output state, and the output state refers to generating a drive signal according to the trigger signal; and a discharge transistor, connected to the plurality of controllable drive units, and configured to be turned on under a drive of the drive signal so as to discharge an electrostatic charge to the ground pad.

An Electrostatic Discharge (ESD) protection circuit includes a first discharge path and a second discharge path. The first discharge path is located between a first potential terminal and a second potential terminal. The second discharge path is located between the first potential terminal and the second potential terminal, and is connected to the first discharge path in parallel. The first discharge path and the second discharge path are used for discharging electrostatic charges. At least one of the first discharge path and the second discharge path includes a Silicon Controlled Rectifier (SCR).

In the examples provided herein, an electrostatic discharge (ESD) recording circuit has a first memristive element coupled to a pin of an integrated circuit. The first memristive element switches from a first resistance to a second resistance when an ESD event occurs at the pin, and the first resistance is less than the second resistance. The ESD recording circuit also has shunting circuitry to shunt energy from an additional ESD event away from the first memristive element.

Example devices and methods for compensating for monitoring a surge protection device are provided. In some embodiments, a device is configured to couple to a surge protection device. The device comprises a processor that is capable of sending a DC current signal. A serial data interface is electrically connected to the processor and includes at least one shift register. The device also comprises a multiplexer coupled to the serial data interface. The serial data interface is operable to direct the DC current through the multiplexer. The device also comprises an analog to digital converter (optionally embedded within the processor) that is operable to output a digital signal corresponding to a voltage induced by the DC current signal. Returned DC signals represent surge protection device's health and a multitude of other surge module information.

Electrostatic discharge (ESD) protection is provided in circuits which use of a tunneling field effect transistor (TFET) or an impact ionization MOSFET (IMOS). These circuits are supported in silicon on insulator (SOI) and bulk substrate configurations to function as protection diodes, supply clamps, failsafe circuits and cutter cells. Implementations with parasitic bipolar devices provide additional parallel discharge paths.

A device is disclosed herein. The device includes a bias generator, an ESD driver, and a logic circuit. The bias generator includes a first transistor. The ESD driver includes a second transistor and a third transistor coupled to each other in series. The logic circuit is configured to generate a logic control signal. A first terminal of the first transistor is configured to receive a reference voltage signal, a control terminal of the first transistor is configured to receive a detection signal in response to an ESD event being detected, a second terminal of the first transistor is coupled to a control terminal of the third transistor, and a control terminal of the second transistor is configured to receive the logic control signal.

An ESD protection circuit is provided, including a negative ESD protection module and a positive ESD protection module, where the negative ESD protection module includes a first resistor, a charging capacitor, a first field effect transistor, and a second field effect transistor, and the positive ESD protection module includes a fourth field effect transistor. When a negative ESD event occurs, there is a comparatively large transient voltage at a gate of a P-type enhanced GaN power device relative to a source of the P-type enhanced GaN power device. Therefore, a displacement current from the source to the gate of the P-type enhanced GaN power device is generated on the charging capacitor. A voltage drop generated by the displacement current on the first resistor may enable the first field effect transistor and the second field effect transistor to form a path when the first field effect transistor is turned on.

An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include electrostatic discharge (ESD) protection circuit structures. The ESD protection circuit structures may be formed in regions other than the region that the IGFETs are formed as well as in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming ESD protection circuit structures in regions below the IGFETs, an older process technology may be used and device size may be decreased. Furthermore, planar IGFETs of FinFETs may be formed in other regions to decrease device size and improve costs.

Disclosed is a BRCT clamping absorption circuit with short circuit protection, which relates to the technical field of short-circuit protection, includes a load module, a short-circuit detection module, a short-circuit protection module, a spike absorption module, a rectifying module, a clamping module and a main control module, wherein, the spike absorption module is connected with the load module, the rectifying module is connected with the spike absorption module, and the clamping module is connected with the rectifying module to form a clamping absorption protection for a spike voltage; the main control module is connected with the short-circuit detection module, and is used for controlling the on-off of a load regulator according to the short-circuit signal.