In some examples, an electrical power system includes a power source and a load modulator configured to receive power from the power source and to deliver power to a load zone. The electrical power system also includes a controller configured to determine a software-controlled power flow limit for the load zone. The controller is further configured to receive information indicating the power delivered to the load zone and to cause the power delivered to the load zone to remain below the software-controlled power flow limit.

In some examples, an electrical power system includes a power source and a load modulator configured to receive power from the power source and to deliver power to a load zone. The electrical power system also includes a controller configured to determine a software-controlled power flow limit for the load zone. The controller is further configured to receive information indicating the power delivered to the load zone and to cause the power delivered to the load zone to remain below the software-controlled power flow limit.

The present disclosure provides an electrostatic discharge (ESD) protection structure, an ESD protection circuit, and a chip. The ESD protection structure includes a semiconductor substrate, a first N-type well, a first P-type well, a first N-type doped portion, a first P-type doped portion, a second N-type doped portion, and a second P-type doped portion. The semiconductor substrate includes a first integrated region. The first N-type well is located in the first integrated region. The first P-type well is located in the first integrated region. The first N-type doped portion is located in the first N-type well. The first P-type doped portion is located in the first N-type well. The second N-type doped portion is located in the first P-type well. The second P-type doped portion is located on a side of the second N-type doped portion away from the first N-type well.

A method of protecting a superconducting magnet from quenches, the superconducting magnet having at least one primary coil comprising high temperature superconductor, HTS, material. A secondary HTS tape is provided, the secondary HTS tape being in proximity to and electrically insulated from the primary coil, and being configured to cease superconducting at a lower temperature than the primary coil during operation of the magnet. A loss of superconductivity in the secondary HTS tape is detected. In response to said detection, energy is dumped from the primary coil into an external resistive load.

A method of protecting a superconducting magnet from quenches, the superconducting magnet having at least one primary coil comprising high temperature superconductor, HTS, material. A secondary HTS tape is provided, the secondary HTS tape being in proximity to and electrically insulated from the primary coil, and being configured to cease superconducting at a lower temperature than the primary coil during operation of the magnet. A loss of superconductivity in the secondary HTS tape is detected. In response to said detection, energy is dumped from the primary coil into an external resistive load.

An apparatus for regulating a slew time of an output voltage of a motor driver system includes a gate current control circuit which has a first input coupled to receive a target slew time and a second input coupled to receive a slew time. The gate current control circuit provides an incremented gate current if the slew time is greater than the target slew time and provides a decremented gate current if the slew time is less than the target slew time. The apparatus includes a gate driver which has a first input coupled to receive a PWM signal and a second input coupled to receive the gate current. The gate driver provides a gate drive signal.

A system of surge suppressor units is connected at multiple locations on a power transmission and distribution grid to provide grid level protection against various disturbances before such disturbances can reach or affect facility level equipment. The surge suppressor units effectively prevent major voltage and current spikes from impacting the grid. In addition, the surge suppressor units include various integration features which provide diagnostic and remote reporting capabilities required by most utility operations. As such, the surge suppressor units protect grid level components from major events such as natural geomagnetic disturbances (solar flares), extreme electrical events (lightning) and human-generated events (EMPs) and cascading failures on the power grid.

A system of surge suppressor units is connected at multiple locations on a power transmission and distribution grid to provide grid level protection against various disturbances before such disturbances can reach or affect facility level equipment. The surge suppressor units effectively prevent major voltage and current spikes from impacting the grid. In addition, the surge suppressor units include various integration features which provide diagnostic and remote reporting capabilities required by most utility operations. As such, the surge suppressor units protect grid level components from major events such as natural geomagnetic disturbances (solar flares), extreme electrical events (lightning) and human-generated events (EMPs) and cascading failures on the power grid.

Switch for connecting field apparatuses and device for galvanically isolating at least one apparatus which is connectable to a 2-wire Ethernet bus system includes an uplink and a downlink PHY interface device that each have a transmitting unit and a receiving unit that has two output terminals for providing a received ternary-coded signal as differential signal, includes an uplink and a downlink signal split device that are each connected to the output terminals of an assigned receiving unit and are configured to split a ternary-coded signal provided as differential signal into two binary coded signals, and includes an uplink and a downlink optocoupler device that are each connected to an assigned signal split device and are configured to transfer two received binary-coded signals to a transmitting unit of an assigned PHY interface device.

A radio frequency integrated circuit (RFIC) device includes: a first RF input/output (I/O) terminal; a second RF I/O terminal, where the first and the second RF I/O terminals are configured to transmit or receive an RF signal; a capacitor coupled between the first and the second RF I/O terminals; a first coil coupled between the first and the second RF I/O terminals, where the first coil is configured to provide ESD protection to the capacitor during a first ESD event; and a fast transient ESD protection circuit coupled between the first and the second RF I/O terminals, where the fast transient ESD protection circuit is configured to provide ESD protection to the capacitor during a second ESD event different from the first ESD event, where a first rise time of the first ESD event is longer than a second rise time of the second ESD event.