A driving circuit providing a driving signal at a driving terminal to drive a power switch. The driving signal has a first driving period and a second driving period. Both the first driving period and the second driving period have a first driving time interval. The driving circuit has a first equivalent on resistor established during the first driving time interval and located between a first voltage node and the driving terminal. The first equivalent on resistor has a first equivalent on resistance during the first driving time interval of the first driving period and has a second equivalent on resistance during the first driving time interval of the second driving period. The first equivalent on resistance and the second equivalent on resistance are not equal.

A low EMI driver apparatus includes: a driver circuit configured to generate a driving signal according to a switch control signal, so as to drive at least one switch; and a driving strength control circuit configured to randomly control a driving strength of the driver circuit, thereby reducing an EMI generated when the at least one switch is driven according to the driving signal. In a specific form of the low EMI driver apparatus, the at least one switch includes plural switches, and the low EMI driver apparatus further includes: a dead time control circuit configured to randomly control a dead time between ON times of the plural switches, so as to reduce the EMI generated when the switches are driven according to the driving signal.

A power module for operating a vehicle, in particular an electric vehicle and/or a hybrid vehicle, comprising numerous semiconductor components, which form at least one topological switch; an input contact for supplying an input current to the semiconductor components; a control electronics for controlling the semiconductor components, to generate an output current based on the input current; an output contact for outputting the output current; wherein the control electronics is configured to set a gate current for one of the semiconductor components based on one or more status parameters for the semiconductor component.

A voltage converter includes an input voltage line; an inductor coupled to the input voltage line; transistors coupled to the inductor; an output voltage line coupled to at least one of the transistors; a current sensor coupled to at least one of the input voltage line, the inductor, or the output voltage line; and a comparator coupled between the current sensor and the transistors. A DC-DC converter may include a voltage converter having an inductor and a plurality of transistors and configured to convert an input voltage into a power voltage and output the power voltage to an output terminal, an input current sensor configured to sense the input current of the converter, and a controller configured to change the slew rate of an inductor voltage in response to the input current of the converter and a preset reference current.

An object is to provide a technique capable of bringing a switching time point of a gate drive condition close to an appropriate switching time point. A semiconductor switching element drive circuit includes a logic circuit that inverts a level of an output signal based on a divided voltage of an output voltage of a semiconductor switching element, and a switching circuit. The switching circuit switches a gate drive condition of the semiconductor switching element during a turn-off operation from a first gate drive condition to a second gate drive condition in which a switching speed is lower than that of the first gate drive condition based on the output signal from the logic circuit.

A hybrid gate driver circuit includes a field effect transistor (FET) drive terminal, a switching node terminal, a transistor, and a capacitor. The transistor includes a first terminal coupled to the FET drive terminal, and a second terminal coupled to ground. The capacitor includes a first terminal coupled to the switching node terminal, and a second terminal coupled to a third terminal of the transistor.

A power converter includes: a switching transistor, a transformer, a control circuit; the control circuit is configured to determine a target voltage in a process that the switching transistor is driven to conduct; the target voltage can represent a voltage change of an input terminal of the switching transistor; when the target voltage starts to drop but is higher than a reference voltage, drive a control terminal of the switching transistor with a first driving current; when the target voltage decreases to be lower than the reference voltage, drive the switching transistor with a second driving current; the second driving current is higher than the first driving current; the switching transistor is driven by the first driving current for part or all of the time before entering the Miller plateau stage, and is driven by the second driving current after starting to enter the Miller plateau stage.

A gate drive circuit according to an embodiment includes: a voltage detector that detects a voltage between a first terminal and a second terminal of a switching device; a delay circuit that outputs, with a delay for a predetermined time, a detected value of the voltage obtained from the voltage detector; and a first off-mode drive circuit and a second off-mode drive circuit that apply a control signal to a control terminal of the switching device for turning off the switching device, wherein the first off-mode drive circuit turns off the switching device faster than the second off-mode drive circuit, and stops its operation to turns off the switching device when the delayed voltage value output from the delay circuit exceeds a predetermined threshold value.

Switching circuits, half-bridge power converters, and methods for operating a switching circuit including a switching transistor coupled to a load. The method includes applying, with a driver, a gate voltage to the switching transistor. The method also includes generating, with a feedback capacitor, a feedback current based on a change in a voltage sensed at a drain terminal of the switching transistor when the switching transistor turns on. The method further includes applying the feedback current to the driver to limit the gate voltage applied to the switching transistor. The method also includes adjusting, with a controller, a switching slew rate of the switching transistor by draining an amount of the feedback current.

A method for controlling an electrical switch using a driver waveform, wherein the driver waveform comprises: a first time period, T.sub.1, associated with a first current, I.sub.G_high; a second time period, T.sub.2, associated with a second current, I.sub.G_low; wherein: the first current of the driver waveform, I.sub.G_high, is larger than the second current of the driver waveform, I.sub.G_low; and the first time period, T.sub.1, has a first duration and the second time period, T.sub.2, has a second duration. The method comprising: determining an optimised first duration by repeatedly modifying the first duration until an overshoot in an output waveform generated by switching the electrical switch using the driver waveform is less than a threshold; determining an optimised second duration based on the optimised first duration; and switching the electrical switch using the optimised first duration and the optimised second duration.