A single-phase power converter is disclosed for converting a direct current power source to an alternating current power across first and second output terminals, which may be connected to a split-phase system having a first-phase load connected between one phase and a second-phase load connected between the other phase. When the loads are not balanced, the single-phase power converter provides a differential current to compensate for the imbalance.

A multiphase converter is disclosed. The multiphase converter comprises multiple phase legs. Each leg has a combination of power semiconductors. The multiphase converter further comprises a terminal current sensor configured to generate output signals indicating a terminal current flowing through the multiphase converter. The multiphase converter further comprises a plurality of current sensors configured to generate output signals indicating low side switch phase current of each phase leg. The multiphase converter further comprises a low pass filter for filtering out high frequency component of the low side switch current signal for each phase leg.

An interlocking adapter in one aspect of the present disclosure includes a current path, an electric load, a switch, and a controller. The controller turns on and off the switch in synchronization with a change of an alternating-current voltage received from an electric outlet of an electric apparatus in response to reception of an interlocking command signal from a working machine so as to supply a load current from the electric outlet to the electric load. The controller turns on and off the switch at a specified ratio of a time every ½ cycle of the alternating-current voltage.

An integrated circuit. The integrated circuit comprises a timebase generator and a switch mode direct current-to-direct current (DC-to-DC) converter coupled to the timebase generator. The timebase generator comprises a linear feedback shift register (LFSR) having an output and a logic circuit comprising a first logic inverter, a first AND logic gate, and a first multiplexer, wherein the first logic inverter has an input coupled to a most significant bit of the output of the LFSR, wherein the first AND logic gate has a first input coupled to a second most significant bit of the output of the LFSR and a second input coupled to an output of the first logic inverter, wherein a selector input of the first multiplexer is coupled to an output of the first AND logic gate.

A circuit for controlling an input current, the circuit includes a first input port configured to receive the input current. A current detector detects an input current value of the input current and generates a control signal indicative of the input current value. A first output port outputs an output current to a load. A second output port receives the output current from the load. A control circuit provides a low-impedance path in parallel with the load in response to the control signal indicating the input current value is below a threshold value.

An electronic circuit is disclosed. The electronic circuit includes: a half-bridge with a first transistor device (1) and a second transistor device (1a); a first biasing circuit (3) connected in parallel with a load path of the first transistor device (1) and comprising a first electronic switch (31); a second biasing circuit (3a) connected in parallel with a load path of the second transistor device (1a) and comprising a second electronic switch (31a); and a drive circuit arrangement (DRVC). The drive circuit arrangement (DRVC) is configured to receive a first half-bridge input signal (Sin) and a second half-bridge input signal (Sina), drive the first transistor device (1) and the second electronic switch (31a) based on the first half-bridge input signal (Sin), and drive the second transistor device (1a) and the first electronic switch (31) based on the second half-bridge input signal (Sina).

A voltage converter includes a voltage conversion circuit, a pulse width modulation (PWM) signal generating module, a feedback controlling module, and a subtractor. The voltage conversion circuit is configured to convert an input voltage to an output voltage according to a PWM signal. The PWM signal generating module is configured to generate the PWM signal according to a control signal. The feedback controlling module is configured to generate the control signal according to a feedback signal. The subtractor is configured to subtract a first reference voltage by the output voltage, to generate the feedback signal. The phase of an AC component of the first reference voltage is substantially opposite to the phase of the input voltage.

A first filter outputs a first signal in response to receiving an input signal. The first signal has a first state in response to the input signal reaching a first threshold voltage on a leading edge of the input signal, and a second state in response to the input signal reaching the first threshold voltage on a trailing edge of the input signal. A second filter outputs a second signal in response to receiving the input signal. The second signal has the first state in response to the input signal reaching a second threshold voltage on the leading edge of the input signal, and the second state in response to the input signal reaching the second threshold voltage on the trailing edge of the input signal. A detection circuit determines, based on times when the first and second thresholds are reached, whether the input signal is received from a triac.

An embodiment DC to DC conversion circuit comprises a DC to DC converter and a regulation circuit. The regulation circuit comprises a comparator configured to detect, during a discharge phase of the DC to DC converter, an overshoot period during which an output voltage of the DC to DC converter exceeds a target voltage, and a timer configured to measure a duration of the overshoot period.

Embodiments described herein provide a zero-crossing detector (ZCD) for a direct current to direct current (DC-DC) converter. The ZCD includes a ZCD integrator configured to receive a switch voltage and an output voltage of a power stage of the DC-DC converter and to generate a zero-crossing detect signal based, at least in part, on the received switch voltage and output voltage, where the zero-crossing detect signal is configured to indicate an output current in an output inductor of the power stage of the DC-DC converter is approximately zero. The ZCD may also include a ZCD offset calibrator configured to receive the switch voltage and generate a ZCD calibration offset based, at least in part, on the received switch voltage, where the ZCD integrator is configured to generate the zero-crossing detect signal based, at least in part, on the ZCD calibration offset.