A method of controlling a multi-phase power converter having a plurality of power stage circuits coupled in parallel, can include: obtaining a load current of the multi-phase power converter; enabling corresponding power stage circuits to operate in accordance with the load current, such that a switching frequency is maintained within a predetermined range when the load current changes; and controlling the power stage circuits to operate under different modes in accordance with the load current, such that the switching frequency is maintained within the predetermined range when the load current changes.

In an example, a method includes storing a pending PWM pulse for a switching voltage regulator. The method also includes determining a switching voltage regulator is operating in a current limit mode, where an inductor current is above a current limit threshold. The method includes providing a predetermined number of PWM pulses in the current limit mode. The method also includes, responsive to providing the predetermined number of PWM pulses, ceasing storage of pending PWM pulses for the switching voltage regulator.

This application relates to computing circuitry, and in particular to analogue computing circuitry suitable for neuromorphic computing. An analogue computation unit for processing data is supplied with a first voltage from a voltage regulator which is operable in a sequence of phases to cyclically regulate the first voltage. A controller is configured to control operation of the voltage regulator and/or the analogue computation unit, such that the analogue computation unit processes data during a plurality of compute periods that avoid times at which the voltage regulator undergoes a phase transition which is one of a predefined set of phase transitions between defined phases in said sequence of phases. This avoids performing computation operations during a phase transition of the voltage regulator that could result in a transient or disturbance in the first voltage, which could adversely affect the computing.

A control circuit for a multiphase buck converter includes a regulator circuit and a plurality of phase control circuits. The regulator circuit generates a regulation signal based on a feedback signal and a reference signal, and each phase control circuit receives a current sense signal and generates a respective PWM signal based on the respective current sense signal and the regulation signal. The control circuit includes a first selector circuit and a second selector circuit configured to receive a selection signal and selectively connect each phase control circuit of a subset of the phase control circuits to a PWM signal for driving a respective stage of the multiphase buck converter, and to a current sense signal provided by the respective stage of the multiphase buck converter. A selection control circuit generates the selection signal in order to connect the phase control circuits to different stages of the multiphase buck converter.

A method for operating a gate driver system includes measuring a first parameter according to a first priority schedule synchronously to a first edge of a switching signal generated by a gate driver integrated circuit and having a variable duty cycle. The method includes after measuring the first parameter of the gate driver system and prior to a second edge of the switching signal, measuring at least a second parameter of the gate driver system according to a first round-robin schedule synchronously to the first edge of the switching signal.

This disclosure describes systems, methods, and apparatus for reducing current imbalances between phases in a multi-phase converter as well as reducing instances of particular phases switching twice within a single pulse-width modulated cycle, or other time period. Phases that have not switched for a longest period of time can be compared to see if swapping their firing patterns would reduce current imbalances, and if so, then those firing patterns can be swapped.

An electrical conversion system includes an inverter arranged according to a multilevel type topology with k arms and a command device for cut-off against an electrical overload, connected to a set of first intermediate lines to measure a first intermediate continuous voltage. The cut-off command device is configured to determine a fault by detecting if the first measured intermediate continuous voltage is outside of a nominal voltage variation range [Vmax1, Vmin1] of the first intermediate voltage and to transmit a generalised opening command signal for an opening of the electronic commutation switches of each arm when the fault is determined.

A method of controlling a multi-phase power converter having a plurality of power stage circuits coupled in parallel, can include: obtaining a load current of the multi-phase power converter; enabling corresponding power stage circuits to operate in accordance with the load current, such that a switching frequency is maintained within a predetermined range when the load current changes; and controlling the power stage circuits to operate under different modes in accordance with the load current, such that the switching frequency is maintained within the predetermined range when the load current changes.

A driver device, a method for monitoring a driver device, and a power supply device are disclosed. The driver device includes a controller and a driver module. The driver module includes a voltage divider loop and a plurality of drivers. The voltage divider loop includes a pull-down resistor and one or more corresponding resistors connected to each of the plurality of drivers, where the pull-down resistor and the one or more corresponding resistors are coupled to a power supply via a first node, and the first node is coupled to the controller.

This application relates to computing circuitry, and in particular to analogue computing circuitry suitable for neuromorphic computing. An analogue computation unit for processing data is supplied with a first voltage from a voltage regulator which is operable in a sequence of phases to cyclically regulate the first voltage. A controller is configured to control operation of the voltage regulator and/or the analogue computation unit, such that the analogue computation unit processes data during a plurality of compute periods that avoid times at which the voltage regulator undergoes a phase transition which is one of a predefined set of phase transitions between defined phases in said sequence of phases. This avoids performing computation operations during a phase transition of the voltage regulator that could result in a transient or disturbance in the first voltage, which could adversely affect the computing.